Output circuit of semiconductor device

• US 20080054937A1
• Filed: 08/27/2007
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kinoshita, Hiroto, Fujisawa, Hiroki
• Granted Patent: US 8,085,061 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS

Abstract

An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.

Claims

1. An output circuit of a semiconductor device comprising a plurality of unit buffers connected in parallel, each unit buffer having transistor and resistor connected in series between a power source terminal and an output terminal, wherein

ON resistance values of the transistors included in the plurality of unit buffers are mutually substantially the same, and out of the plurality of unit buffers, resistance values of the resistors included in at least two unit buffers are different from each other.

2. The output circuit of a semiconductor device as claimed in claim 1, further comprising an output control circuit that selects the unit buffer to be used, wherein the output control circuit selects, with priority, a unit buffer in which the resistance value of the resistor is higher.

3. The output circuit of a semiconductor device as claimed in claim 1, wherein a difference between the resistance values of the resistors included in the at least two unit buffers is larger than the value of the power source resistance present between the power source terminal and the output circuit.

4. The output circuit of a semiconductor device as claimed in claim 3, wherein the difference is about two times of the power source resistance.

14. The output circuit of a semiconductor device as claimed in claim 1, further comprising a replica buffer connected to a calibration terminal and having a configuration substantially the same as that of at least one of the unit buffers.

15. The output circuit of a semiconductor device as claimed in claim 14, further comprising a controller that adjusts the impedance of the replica buffer, wherein the controller applies the impedance control applied to the replica buffer in common to the unit buffers.

5. An output circuit of a semiconductor device comprising:

a first output buffer including one unit buffer having a series circuit of transistor and resistor;

a second output buffer having m unit buffers connected in parallel, each unit buffer having a series circuit of transistor and resistor; and

a third output buffer having n unit buffers connected in parallel, each unit buffer having a series circuit of transistor and resistor, wherein

ON resistance values of the transistors included in the first to the third output buffers are mutually substantially the same,

resistance values of the resistors included in the second output buffer are mutually substantially the same,

resistance values of the resistors included in the third output buffer are mutually substantially the same, and

resistance values of at least the two resistors included in the first to the third output buffers are different from each other.

6. The output circuit of a semiconductor device as claimed in claim 5, wherein the resistance values of the resistor included in the first output buffer is different from the resistance values of the resistors included in the third output buffer.

7. The output circuit of a semiconductor device as claimed in claim 5, wherein the resistance values of the resistors included in the second output buffer are different from the resistance values of the resistors included in the third output buffer.

8. The output circuit of a semiconductor device as claimed in claim 6, wherein the resistance values of the resistors included in the third output buffer are lower than at least one of the resistance values of the resistors included in the first and the second output buffers.

9. The output circuit of a semiconductor device as claimed in claim 5, wherein the resistance values of the resistor included in the first output buffer are substantially the same as the resistance values of the resistors included in the second output buffer.

10. The output circuit of a semiconductor device as claimed in claim 5, wherein m is equal to 2 and n is equal to 3,

when one unit buffer is used, the first output buffer is selected,

when two unit buffers are used, the second output buffer is selected,

when three unit buffers are used, the first and the second output buffers are selected simultaneously,

when four unit buffers are used, the first and the third output buffers are selected simultaneously,

when five unit buffers are used, the second and the third output buffers are selected simultaneously, and

when six unit buffers are used, the first to the third output buffers are selected simultaneously.

11. The output circuit of a semiconductor device as claimed in claim 5, further comprising a fourth output buffer including one unit buffer having a series circuit of transistor and resistor, wherein

ON resistance values of the transistors included in the first to the fourth output buffers are mutually substantially the same, and

resistance values of the resistor included in the fourth output buffer are different from resistance values of the resistors included in the first to the third output buffers.

12. The output circuit of a semiconductor device as claimed in claim 11, wherein resistance values of the resistors included in the fourth output buffer are lower than resistance values of the resistors included in the first to the third output buffers.

13. The output circuit of a semiconductor device as claimed in claim 11, wherein when seven unit buffers are selected, the first to the fourth output buffers are selected simultaneously.

16. A data processing system comprising a data processor and a semiconductor memory device,

wherein the semiconductor memory device includes an output circuit having a plurality of unit buffers connected in parallel, each unit buffer having transistor and resistor connected in series between a power source terminal and an output terminal, wherein

ON resistance values of the transistors included in the plurality of unit buffers are mutually substantially the same, and out of the plurality of unit buffers, resistance values of the resistors included in at least two unit buffers are different from each other.