DELAY LOCKED LOOP HAVING CHARGE PUMP GAIN INDEPENDENT OF OPERATING FREQUENCY

• US 20080054963A1
• Filed: 09/12/2007
• Published: 03/06/2008
• Est. Priority Date: 04/12/2006
• Status: Abandoned Application

• Current Assignee: Charles Masenas
• Original Assignee: Charles Masenas
• Inventors: Masenas, Charles
• Application Number:
  US11/854,046
• Publication Number:
  US 20080054963A1
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop

Abstract

A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A charge pump is disclosed for providing a charge to a capacitive element on a voltage controlled delay line, wherein the charge is independent of a control voltage step cycle time of the DLL, the charge pump includes: a charge/dump signal generation stage that generates a charge signal and a dump signal during each period of a reference clock signal; a first switched capacitor stage that charges a first capacitor in response to the charge signal and dumps a positive charge from the first capacitor in response to the dump signal; a second switched capacitor stage that charges a second capacitor in response to the charge signal and dumps a negative charge from the second capacitor in response to the dump signal; and an output stage that selectively loads either the positive charge or the negative charge to the capacitive element on the voltage controlled delay line in response to an input signal from a phase detector.

Claims

1. A delay locked loop (DLL) circuit having a charge pump gain independent of frequency, comprising:

a switched capacitor charge pump configured with an “

H”

driver output stage;

a phase detector;

a capacitor; and

a voltage controlled delay line.

2. A delay locked loop (DLL) circuit having a charge pump gain independent of frequency, comprising:

a switched capacitor charge pump configured with an “

H”

driver output stage that feeds a signal into a first switched capacitor stage configured for dumping a charge into an output stage from a first capacitor;

a phase detector;

a capacitor; and

a voltage controlled delay line.

3. The delay lock loop (DLL) of claim 2, wherein the switched capacitor charge pump generates a charge signal and a dump signal during each period of a reference clock that is fed into the first switched capacitor stage.

4. The delay lock loop (DLL) of claim 3, wherein the charge comprises a positive charge.