CIRCUITRY FOR LATCHING
First Claim
1. A method for latching an input signal, the method comprising:
- providing an output signal;
providing a control signal having a first edge and a second edge; and
providing the input signal, wherein the input signal is setup with reference to the control signal, and wherein the input signal is held with reference to the control signal,wherein the setup of the input signal with reference to the control signal is to the first edge of the control signal,wherein the holding of the input signal with reference to the control signal is independent of the second edge of the control signal, andwherein the output signal goes to a predetermined state in response to the second edge of the control signal.
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Accused Products
Abstract
Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.
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Citations
20 Claims
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1. A method for latching an input signal, the method comprising:
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providing an output signal; providing a control signal having a first edge and a second edge; and providing the input signal, wherein the input signal is setup with reference to the control signal, and wherein the input signal is held with reference to the control signal, wherein the setup of the input signal with reference to the control signal is to the first edge of the control signal, wherein the holding of the input signal with reference to the control signal is independent of the second edge of the control signal, and wherein the output signal goes to a predetermined state in response to the second edge of the control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A latch circuit having a first input for receiving an input signal, having a second input for receiving a control signal, and having an output for providing an output signal, the latch circuit comprising:
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a first circuit portion (90) for gating the input signal to the output of the latch when the control signal is negated; a second circuit portion (94) coupled to the first circuit portion, the second circuit portion receives the input signal and selectively gates the input signal to the first circuit portion when the control signal is asserted; and a third circuit portion (92) coupled to the first circuit portion, said third circuit portion holding the input value for the first circuit portion when the control signal is asserted. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A latch circuit having a first input for receiving an input signal, having a second input for receiving a control signal, and having an output for providing an output signal, the latch circuit comprising:
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a first PMOS transistor (21, 121, 221) having a first current electrode, having a control electrode coupled to receive the first input signal, and having a second current electrode; a first NMOS transistor (31, 131, 231) having a first current electrode coupled to the second current electrode of the first PMOS transistor and coupled to a first node (72, 172, 272), having a control electrode coupled to receive the first input signal, and having a second current electrode; a second PMOS transistor (22, 122, 222) having a first current electrode coupled to a first power supply voltage (VDD), having a control electrode coupled to a second node (76, 176, 276), and having a second current electrode coupled to the first current electrode of the first PMOS transistor; a second NMOS transistor (32, 132, 232) having a first current electrode coupled to the second current electrode of the first NMOS transistor, having a control electrode coupled to a third node (78, 178, 278), and having a second current electrode coupled to a second power supply voltage (VSS); a third PMOS transistor (23, 123, 223) having a first current electrode coupled to the first power supply voltage (VDD), having a control electrode coupled to the third node, and having a second current electrode coupled to the first node; a third NMOS transistor (33, 133, 233) having a first current electrode coupled to the first node, having a control electrode coupled to the second node, and having a second current electrode coupled to the second power supply voltage (VSS); a first circuit portion ( 40, 50) (141, 142, 144) (240, 250) coupled to the output of the latch circuit for receiving the output signal, coupled to the second input of the latch circuit for receiving the control signal, and coupled to the second node; a second circuit portion (90, 190, 290) having an output coupled to the output of the latch circuit; and a third circuit portion (41, 42, 60) (140, 150) (241, 242, 260) having an input coupled to the second input of the latch circuit for receiving the control signal, and having an output coupled to the third node. - View Dependent Claims (18, 19, 20)
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Specification