CIRCUITRY FOR LATCHING

• US 20080054975A1
• Filed: 08/30/2006
• Published: 03/06/2008
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramaraju, Ravindraraj
• Granted Patent: US 7,495,493 B2
• Time in Patent Office: Days
• US Class Current: 327/218
• CPC Class Codes: H03K 3/356173 with synchronous operation

Abstract

Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.

Claims

1. A method for latching an input signal, the method comprising:

providing an output signal;

providing a control signal having a first edge and a second edge; and

providing the input signal, wherein the input signal is setup with reference to the control signal, and wherein the input signal is held with reference to the control signal,

wherein the setup of the input signal with reference to the control signal is to the first edge of the control signal,

wherein the holding of the input signal with reference to the control signal is independent of the second edge of the control signal, and

wherein the output signal goes to a predetermined state in response to the second edge of the control signal.

2. A method as in claim 1, wherein the predetermined state comprises a reset state.

3. A method as in claim 1, wherein the control signal comprises a clock signal.

4. A method as in claim 1, wherein when the control signal is asserted and the input signal is low, the input signal is allowed through to affect the output signal, and wherein when the control signal is asserted and the input signal is high, the input signal is not allowed through to affect the output signal.

5. A method as in claim 1, wherein when the control signal is asserted, the output signal is held approximately constant by a holding circuit.

6. A method as in claim 5, wherein when the control signal is negated, the output signal goes to the predetermined state.

7. A method as in claim 6, wherein when the control signal is negated, the output signal is no longer held at the predetermined state by the holding circuit.

8. A method as in claim 1, wherein the input signal has a hold time, and wherein during the hold time of the input signal the input signal is to remain transitionless, and wherein the hold time comprises a low hold time for the input signal remaining low, and a high hold time for the input signal remaining high.

9. A method as in claim 8, wherein the low hold time and the high hold time are different.

10. A latch circuit having a first input for receiving an input signal, having a second input for receiving a control signal, and having an output for providing an output signal, the latch circuit comprising:

a first circuit portion (90) for gating the input signal to the output of the latch when the control signal is negated;

a second circuit portion (94) coupled to the first circuit portion, the second circuit portion receives the input signal and selectively gates the input signal to the first circuit portion when the control signal is asserted; and

a third circuit portion (92) coupled to the first circuit portion, said third circuit portion holding the input value for the first circuit portion when the control signal is asserted.

11. A latch circuit as in claim 10, wherein the first circuit portion comprises:

a NAND gate having an output; and

an inverter, having an input coupled to the output of the NAND gate, and having an output for providing the output signal.

12. A latch circuit as in claim 10, wherein the first circuit portion comprises:

a NOR gate having an output for providing the output signal.

13. A latch circuit as in claim 10, wherein the third circuit portion comprises:

a p-channel device having a first current electrode coupled to the first circuit portion; and

an n-channel device having a first current electrode coupled to the first current electrode of the p-channel device.

14. A latch circuit as in claim 10, wherein the second circuit portion allows the input signal through to affect the output signal when the control signal is asserted and the input signal is low, and wherein the second circuit portion prevents the input signal from affecting the output signal when the control signal is asserted and the input signal is high.

15. A latch circuit as in claim 10, wherein the third circuit portion holds an input value of the input signal for the first circuit portion when the control signal is asserted, and the third circuit portion does not hold the input value of the input signal for the first circuit portion when the control signal is negated.

16. A latch circuit as in claim 10, wherein when the control signal is asserted, selective gating by the second circuit portion is dependent upon an input value of the input signal.

17. A latch circuit having a first input for receiving an input signal, having a second input for receiving a control signal, and having an output for providing an output signal, the latch circuit comprising:

a first PMOS transistor (21, 121, 221) having a first current electrode, having a control electrode coupled to receive the first input signal, and having a second current electrode;

a first NMOS transistor (31, 131, 231) having a first current electrode coupled to the second current electrode of the first PMOS transistor and coupled to a first node (72, 172, 272), having a control electrode coupled to receive the first input signal, and having a second current electrode;

a second PMOS transistor (22, 122, 222) having a first current electrode coupled to a first power supply voltage (VDD), having a control electrode coupled to a second node (76, 176, 276), and having a second current electrode coupled to the first current electrode of the first PMOS transistor;

a second NMOS transistor (32, 132, 232) having a first current electrode coupled to the second current electrode of the first NMOS transistor, having a control electrode coupled to a third node (78, 178, 278), and having a second current electrode coupled to a second power supply voltage (VSS);

a third PMOS transistor (23, 123, 223) having a first current electrode coupled to the first power supply voltage (VDD), having a control electrode coupled to the third node, and having a second current electrode coupled to the first node;

a third NMOS transistor (33, 133, 233) having a first current electrode coupled to the first node, having a control electrode coupled to the second node, and having a second current electrode coupled to the second power supply voltage (VSS);

a first circuit portion ( 40, 50) (141, 142, 144) (240, 250) coupled to the output of the latch circuit for receiving the output signal, coupled to the second input of the latch circuit for receiving the control signal, and coupled to the second node;

a second circuit portion (90, 190, 290) having an output coupled to the output of the latch circuit; and

a third circuit portion (41, 42, 60) (140, 150) (241, 242, 260) having an input coupled to the second input of the latch circuit for receiving the control signal, and having an output coupled to the third node.

18. A latch circuit as in claim 17, wherein the control signal comprises a clock signal.

19. A latch circuit as in claim 17, wherein the latch circuit is used in a cache tag.

20. An integrated circuit comprising the latch circuit as in claim 17.