Clock Generation Circuit and Semiconductor Device Including the Same

• US 20080054976A1
• Filed: 08/27/2007
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami, Kurokawa, Yoshiyuki, Ikeda, Takayuki, Kawae, Daisuke
• Granted Patent: US 8,103,897 B2
• Time in Patent Office: Days
• US Class Current: 327/291
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a receiving circuit, stabilized communication is possible; and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

Claims

1. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the reference clock counter circuit is a circuit which outputs a counter value to the frequency-divider circuit, the counter value being obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is inputted from the reader/writer through the antenna to the edge detection circuit to when the edge detection circuit detects a next edge, and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

4. The clock generation circuit according to claim 1, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

2. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit is a circuit which detects an edge of a signal which is externally inputted,

wherein the reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects the edge to when the edge detection circuit detects a next edge, to the frequency-divider circuit and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

5. The clock generation circuit according to claim 2, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

3. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit includes a first latch circuit, a second latch circuit to which a signal outputted from the first latch circuit is inputted, an inverter circuit to which the signal outputted from the first latch circuit is inputted, and an AND circuit to which a signal outputted from the second latch circuit and a signal outputted from the inverter circuit are inputted,

wherein the AND circuit is a circuit which outputs a reset signal when the signal outputted from the second latch circuit and the signal outputted from the inverter circuit are different,

wherein the reference clock counter circuit is a circuit in which a counter value which is obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit is reset by the reset signal, and which outputs the counter value to the frequency-divider circuit, and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

6. The clock generation circuit according to claim 3, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

7. A semiconductor device for transmitting and receiving a signal wirelessly with a reader/writer, which is provided with an antenna, comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the reference clock counter circuit is a circuit which outputs a counter value to the frequency-divider circuit, the counter value being obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is inputted from the reader/writer through the antenna to the edge detection circuit to when the edge detection circuit detects a next edge, and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

10. The semiconductor device according to claim 7, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

8. A semiconductor device for transmitting and receiving a signal wirelessly with a reader/writer, which is provided with an antenna, comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit is a circuit which detects an edge of a signal inputted from the reader/writer through the antenna,

wherein the reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects the edge to when the edge detection circuit detects a next edge, to the frequency-divider circuit and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

11. The semiconductor device according to claim 8, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

9. A semiconductor device for transmitting and receiving a signal wirelessly with a reader/writer, which is provided with an antenna, comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit includes a first latch circuit, a second latch circuit to which a signal outputted from the first latch circuit is inputted, an inverter circuit to which the signal outputted from the first latch circuit is inputted, and an AND circuit to which a signal outputted from the second latch circuit and a signal outputted from the inverter circuit are inputted,

wherein the AND circuit is a circuit which outputs a reset signal when the signal outputted from the second latch circuit and the signal outputted from the inverter circuit are different,

wherein the reference clock counter circuit is a circuit in which a counter value which is obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit is reset by the reset signal, and which outputs a counter value to the frequency-divider circuit, and

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

12. The semiconductor device according to claim 9, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.