Calibration circuit, semiconductor device including the same, and method of adjusting output characteristics of semiconductor device

• US 20080054981A1
• Filed: 08/16/2007
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Hosoe, Yuki, Kuroki, Koji
• Granted Patent: US 7,755,366 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.

Claims

1. A calibration circuit comprising:

a replica buffer connected to a calibration terminal;

a reference voltage generating circuit that outputs a reference voltage;

a comparing circuit that compares a voltage at the calibration terminal with the reference voltage;

an impedance adjusting circuit that changes an impedance of the replica buffer based on an output of the comparing circuit; and

a reference voltage adjusting circuit that can change a level of the reference voltage outputted from the reference voltage generating circuit.

2. The calibration circuit as claimed in claim 1, wherein the reference voltage generating circuit generates a plurality of reference voltages having mutually different levels, and the reference voltage adjusting circuit selects one of the plurality of reference voltages.

3. The calibration circuit as claimed in claim 2, wherein the reference voltage adjusting circuit includes a selector that selects any one reference voltage from among the plurality of reference voltages based on a selection signal and a selection signal generating unit that generates the selection signal,

wherein the selection signal generating unit includes a nonvolatile memory element.

4. The calibration circuit as claimed in claim 3, wherein the nonvolatile memory element is an electrically writable element.

5. The calibration circuit as claimed in claim 4, wherein the nonvolatile memory element is an antifuse.

6. The calibration circuit as claimed in claim 2, wherein the reference voltage generating circuit includes a high-resistance part and a low-resistance part, and the plurality of reference voltages are taken out from the low-resistance part.

7. The calibration circuit as claimed in claim 6, wherein the high-resistance part includes a diffusion-layer resistor, and the low-resistance part includes a wiring resistor.

8. The calibration circuit as claimed in claim 1, wherein the replica buffer has either a pull-up function or a pull-down function.

9. A semiconductor device including:

a data output terminal;

a calibration terminal;

an output buffer connected to the data output terminal; and

a calibration circuit,

wherein a part of the output buffer has the same circuit configuration as that of the replica buffer, the calibration circuit includes;

a replica buffer connected to the calibration terminal;

a reference voltage generating circuit that outputs a reference voltage;

a comparing circuit that compares a voltage at the calibration terminal with the reference voltage;

an impedance adjusting circuit that changes an impedance of the replica buffer based on an output of the comparing circuit; and

a reference voltage adjusting circuit that can change a level of the reference voltage outputted from the reference voltage generating circuit.

10. The semiconductor device as claimed in claim 9, wherein the output impedance of the output buffer is adjusted by the impedance adjusting circuit.

11. A calibration circuit comprising:

a first replica buffer connected to a calibration terminal;

a second replica buffer that has the same circuit configuration of the first replica buffer;

a third replica buffer that is connected to the second replica buffer;

first and second reference voltage generating circuits that generate first and second reference voltages, respectively;

a first comparing circuit that compares a voltage at the calibration terminal with the first reference voltage;

a second comparing circuit that compares a voltage at a node of the second and the third replica buffers with the second reference voltage;

a first impedance adjusting circuit that changes output impedances of the first and the second replica buffers based on an output of the first comparing circuit;

a second impedance adjusting circuit that changes an output impedance of the third replica buffer based on an output of the second comparing circuit; and

first and second reference voltage adjusting circuits that adjust the first and the second reference voltages, respectively.

12. The calibration circuit as claimed in claim 11, wherein the first and the second replica buffers have one of a pull-up function and a pull-down function, and the third replica buffer has the other one of the pull-up function and the pull-down function.

13. A semiconductor device comprising:

a data output terminal;

a calibration terminal;

an output buffer connected to the data output terminal; and

a calibration circuit,

wherein the output buffer has the same circuit configuration as those of the second and the third replica buffers, the calibration circuit includes;

a first replica buffer connected to the calibration terminal;

a second replica buffer that has the same circuit configuration of the first replica buffer;

a third replica buffer that is connected to the second replica buffer;

first and second reference voltage generating circuits that generate first and second reference voltages, respectively;

a first comparing circuit that compares a voltage at the calibration terminal with the first reference voltage;

a second comparing circuit that compares a voltage at a node of the second and the third replica buffers with the second reference voltage;

a first impedance adjusting circuit that changes output impedances of the first and the second replica buffers based on an output of the first comparing circuit;

a second impedance adjusting circuit that changes an output impedance of the third replica buffer based on an output of the second comparing circuit; and

first and second reference voltage adjusting circuits that adjust the first and the second reference voltages, respectively.

14. The semiconductor device as claimed in claim 13, wherein the first impedance adjusting circuit adjusts the output impedance of one of a pull-up circuit and a pull-down circuit included in the output buffer, and the second impedance adjusting circuit adjusts the output impedance of the other of the pull-up circuit and the pull-down circuit included in the output buffer.

15. An output-characteristic adjusting method of a semiconductor device including a replica buffer connected to a calibration terminal, a reference voltage generating circuit that generates a reference voltage, a comparing circuit that compares a voltage at the calibration terminal with the reference voltage, and an impedance adjusting circuit that changes an output impedance of the replica buffer based on an output of the comparing circuit, the output-characteristic adjusting method comprising:

a first step of adjusting an impedance of the replica buffer;

a second step of measuring an impedance of the replica buffer; and

a third step of adjusting the reference voltage based on the impedance of the replica buffer.

16. The output-characteristic adjusting method of a semiconductor device as claimed in claim 15, wherein at the first step the impedance of the replica buffer is adjusted so that the voltage appearing at the calibration terminal approximately coincides with the reference voltage.

17. The output-characteristic adjusting method of a semiconductor device as claimed in claim 16, wherein at the third step the reference voltage is offset so that the impedance of the replica buffer observed from the external terminal becomes a predetermined value.

18. A data processing system comprising a data processor and a semiconductor device, wherein the semiconductor device includes a calibration circuit,

wherein the calibration circuit having:

a replica buffer connected to a calibration terminal;

a reference voltage generating circuit that outputs a reference voltage;

a comparing circuit that compares a voltage at the calibration terminal with the reference voltage;

an impedance adjusting circuit that changes an impedance of the replica buffer based on an output of the comparing circuit; and

a reference voltage adjusting circuit that can change a level of the reference voltage outputted from the reference voltage generating circuit.