Integrated circuit device and electronic instrument

• US 20080055324A1
• Filed: 08/10/2007
• Published: 03/06/2008
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kiya, Hiroshi, Kodaira, Satoru
• Granted Patent: US 7,590,015 B2
• Time in Patent Office: Days
• US Class Current: 345/530
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/806 by reducing size of decoders
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/816 for an application-specific layout

Abstract

An integrated circuit device includes a data driver block, a memory block, an information storage block in which an address of a defective cell of the memory block is programmed and stored as a defective address, and a switch control circuit which performs control for switching access to the defective cell to access to a redundant cell. A row address of the defective cell having the row address and a column address is stored in the information storage block as the defective address. The switch control circuit performs control for switching access to the defective cell to access to the redundant cell by comparing a row address for display panel access with the defective address during the display panel access and comparing a row address for host access using the row address and a column address with the defective address during the host access.

Claims

1. An integrated circuit device comprising:

at least one data driver block for driving data lines;

at least one memory block which includes memory cells and redundant cells for repairing a defective cell and stores image data supplied to the data driver block;

an information storage block in which an address of the defective cell of the memory block is programmed and stored as a defective address; and

a switch control circuit which performs control for switching access to the defective cell to access to the redundant cell;

a row address of the defective cell having the row address and a column address being stored in the information storage block as the defective address; and

the switch control circuit performing control for switching access to the defective cell to access to the redundant cell by comparing a row address for display panel access with the defective address stored in the information storage block during the display panel access which is access for a display operation of a display panel, and comparing a row address for host access, which uses the row address and a column address, with the defective address stored in the information storage block during the host access which is access from a host to the memory block.

2. The integrated circuit device as defined in claim 1,

wherein the memory block includes:

a memory cell array in which memory cells and redundant cells are disposed;

a row address decoder which decodes a row address and selects a wordline of the memory cell array; and

a column address decoder which decodes a column address and selects a bitline of the memory cell array.

3. The integrated circuit device as defined in claim 2, wherein the row address for the display panel access is input to the row address decoder during the display panel access;

and wherein the row address for the host access is input to the row address decoder and the column address for the host access is input to the column address decoder during the host access.

4. The integrated circuit device as defined in claim 1, comprising:

first to Ith memory blocks (I is an integer equal to or larger than two), each of the first to Ith memory blocks including memory cells and redundant cells for repairing a defective cell;

wherein the first to Ith memory blocks respectively include first to Ith row address decoders; and

wherein, when a defective cell exists in the Kth memory block (1≦

K≦

I) of the first to Ith memory blocks, not only the Kth row address decoder but also the row address decoders other than the Kth row address decoder select wordlines of the redundant cells during the display panel access.

5. The integrated circuit device as defined in claim 4,

wherein first to Ith bank signals for selecting the first to Ith memory blocks are respectively input to the first to Ith row address decoders;

and

wherein, when the Lth bank signal (1≦

L≦

I) has become active and the Lth memory block has been selected during the host access, the Lth row address decoder selects a wordline of the redundant cells, and the row address decoders other than the Lth row address decoder do not select wordlines of the memory cells and the redundant cells.

6. The integrated circuit device as defined in claim 1, wherein the switch control circuit includes:

a first coincidence detection circuit which receives the row address for the display panel access and the defective address from the information storage block, detects whether or not the row address for the display panel access coincides with the defective address, and activates a first switching signal when the row address for the display panel access coincides with the defective address; and

a second coincidence detection circuit which receives the row address for the host access and the defective address from the information storage block, detects whether or not the row address for the host access coincides with the defective address, and activates a second switching signal when the row address for the host access coincides with the defective address.

7. The integrated circuit device as defined in claim 6,

wherein use instruction information which indicates whether or not to use the redundant cells is programmed and stored in the information storage block;

wherein the first coincidence detection circuit receives an instruction signal corresponding to the use instruction information stored in the information storage block, and inactivates the first switching signal when the instruction signal indicates that the redundant cells are not used; and

wherein the second coincidence detection circuit receives the instruction signal, and inactivates the second switching signal when the instruction signal indicates that the redundant cells are not used.

9. The integrated circuit device as defined in claim 1, comprising:

first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along a first direction when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is defined as a first direction and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is defined as a second direction;

wherein the first to Nth circuit blocks include at least one data driver block and at least one memory block.

10. The integrated circuit device as defined in claim 1, wherein image data stored in the memory block is read from the memory block into the data driver block RN times (RN≧

2) in one horizontal scan period, and the redundant cells of at least RN wordlines are provided in the memory block.

17. An electronic instrument comprising:

the integrated circuit device as defined in claim 1;

and

a display panel driven by the integrated circuit device.

8. An integrated circuit device comprising:

at least one data driver block for driving data lines;

at least one memory block which includes memory cells and redundant cells for repairing a defective cell and stores image data supplied to the data driver block;

an information storage block in which an address of the defective cell of the memory block is programmed and stored as a defective address; and

a switch control circuit which performs control for switching access to the defective cell to access to the redundant cell;

a first address of the defective cell, which has an address made up of the first address and a second address, being stored in the information storage block as the defective address; and

the switch control circuit performing control for switching access to the defective cell to access to the redundant cell by comparing a first address for display panel access with the defective address stored in the information storage block during the display panel access which is access for a display operation of a display panel and comparing a first address for host access, which uses an address made up of the first address and a second address, with the defective address stored in the information storage block during the host access which is access from a host to the memory block.

18. An electronic instrument comprising:

the integrated circuit device as defined in claim 8;

and

a display panel driven by the integrated circuit device.

11. An integrated circuit device comprising:

first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along a first direction when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is defined as a first direction and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is defined as a second direction; and

an information storage block in which initial adjustment information for performing an initial adjustment of the circuit block of the integrated circuit device is programmed and stored;

the first to Nth circuit blocks including;

at least one data driver block for driving data lines; and

a logic circuit block which controls the data driver block, the logic circuit block being disposed between the data driver block and the information storage block.

12. The integrated circuit device as defined in claim 11, wherein the information storage block is disposed adjacent to the logic circuit block.

14. The integrated circuit device as defined in claim 11,

wherein the first to Nth circuit blocks include at least one scan driver block for driving scan lines;

and

wherein, when a direction opposite to the second direction is defined as a fourth direction, the information storage block is disposed on the fourth direction side of the scan driver block.

15. The integrated circuit device as defined in claim 11, wherein first to mth storage blocks (m is an integer equal to or larger than two) in which first to mth initial adjustment information is respectively programmed and stored are disposed in the information storage block.

16. The integrated circuit device as defined in claim 11,

wherein the first to Nth circuit blocks include at least one memory block which includes memory cells and redundant cells for repairing a defective cell and stores image data supplied to the data driver block;

and

wherein an address of the defective cell of the memory block is programmed and stored in the information storage block as the initial adjustment information.

19. An electronic instrument comprising:

the integrated circuit device as defined in claim 11;

and

a display panel driven by the integrated circuit device.

13. An integrated circuit device comprising:

first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along a first direction when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is defined as a first direction and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is defined as a second direction; and

an information storage block in which initial adjustment information for performing an initial adjustment of the circuit block of the integrated circuit device is programmed and stored;

the first to Nth circuit blocks including;

at least one data driver block for driving data lines; and

a logic circuit block which controls the data driver block; and

the information storage block being disposed adjacent to the logic circuit block.

20. An electronic instrument comprising:

the integrated circuit device as defined in claim 13;

and

a display panel driven by the integrated circuit device.