VIDEO INTEGRATED CIRCUIT AND VIDEO PROCESSING APPARATUS THEREOF

• US 20080055471A1
• Filed: 04/27/2007
• Published: 03/06/2008
• Est. Priority Date: 08/30/2006
• Status: Abandoned Application

• Current Assignee: Beacon Advanced Technology Company Limited
• Original Assignee: Beacon Advanced Technology Company Limited
• Inventors: Tsui, Kai-Liang
• Application Number:
  US11/741,434
• Publication Number:
  US 20080055471A1
• Time in Patent Office: Days
• US Class Current: 348/565
• CPC Class Codes: H04N 21/2541 Rights Management protecting software against unauthorised usage in a vending or licensing environment G06F21/10; security in data switching network management H04L41/28; security management or policies for network security H04L63/20; access security in wireless networks H04W12/08
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/4367 Establishing a secure communication between the client and a peripheral device or smart card
• CPC Class Codes: H04N 21/835 Generation of protective data, e.g. certificates protecting software against unauthorised usage in a vending or licensing environment G06F21/10
• CPC Class Codes: H04N 21/8358 involving watermark protecting executable software by watermarking G06F21/16; image watermarking in general G06T1/0021; watermarks inserted in still images for transmission purposes H04N1/32144; inserting watermarks during video coding H04N19/467
• CPC Class Codes: H04N 7/163 by receiver means only

Abstract

Both a video integrated circuit that is connected to a video display apparatus for processing and displaying a plurality of video signals, and the video display apparatus thereof, are provided. The video integrated circuit and the video processing apparatus comprise a processor, a video capture unit, a watermark generating unit, a codec, and a video output unit. The video capture unit receives a digital video signal in response to a first signal from the processor to generate a processing signal. The watermark generating unit receives the processing signal in response to a second signal from the processor, and then embeds a watermark into a video corresponding to the processing signal to generate an integrated signal. The codec receives and compresses the integrated signal in response to a third signal from the processor, and then generates a compressed signal. The video output unit outputs the compressed signal to the video display apparatus in response to a fourth signal from the processor.

Claims

1. A video integrated circuit connected to a video display apparatus, comprising:

a processor;

a video capture unit for receiving a digital video signal and generating a processing signal in response to a first signal from the processor;

a watermark generation unit for receiving the processing signal and for embedding a watermark into an image corresponding to the processing signal to generate an integrated signal in response to a second signal from the processor;

a codec for receiving and compressing the integrated signal to generate a compressed signal in response to a third signal from the processor; and

a video output unit for outputting the compressed signal to the video display apparatus in response to a fourth signal from the processor.

2. The video integrated circuit as claimed in claim 1, further comprising an image recognition unit for recognizing the image and generating a recognition result in response to a fifth signal from the processor and for transmitting the recognition result to the processor.

3. The video integrated circuit as claimed in claim 1, further comprising a video encoder between the video output unit and the video display apparatus for encoding the compressed signal from the video output unit and for outputting the encoded compressed signal to the video display apparatus.

4. The video integrated circuit as claimed in claim 3, wherein the video encoder is a video graphics array (VGA) encoder, and the video display apparatus is one of a VGA display apparatus and a liquid crystal display apparatus.

5. The video integrated circuit as claimed in claim 3, wherein the video encoder is a VGA encoder, and the video display apparatus is a TV.

6. The video integrated circuit as claimed in claim 1, further connected to a memory, wherein the video integrated circuit further comprises a memory controller for storing the compressed signal in the memory in response to a sixth signal from the processor.

7. The video integrated circuit as claimed in claim 6, wherein the memory is a static memory, and the memory controller is a static memory controller.

8. The video integrated circuit as claimed in claim 6, wherein the memory is a double data rate (DDR) memory, and the memory controller is a DDR memory controller.

9. The video integrated circuit as claimed in claim 1, further connected to a hard disk, wherein the video integrated circuit further comprises an integrated drive electronics (IDE) controller for storing the compressed signal in the hard disk in response to a seventh signal from the processor.

10. The video integrated circuit as claimed in claim 1, further connected to a peripheral controller interface (PCI) bus, wherein the video integrated circuit further comprises a PCI unit for outputting the compressed signal to the PCI bus in response to an eighth signal from the processor.

11. The video integrated circuit as claimed in claim 1, further connected to a serial advanced technology attachment (SATA) interface, wherein the video integrated circuit further comprises a SATA controller for outputting the compressed signal to the USB port in response to a ninth signal from the processor.

12. The video integrated circuit as claimed in claim 1, further connected to a universal serial bus (USB) port, wherein the video integrated circuit further comprises a USB unit for outputting the compressed signal to the USB port in response to a tenth signal from the processor.

13. The video integrated circuit as claimed in claim 1, further connected to an Ethernet physical layer, wherein the video integrated circuit further comprises an Ethernet medium access control layer for outputting the compressed signal to the Ethernet physical layer in response to an eleventh signal from the processor.

14. The video integrated circuit as claimed in claim 1, further comprises an encryption unit for encrypting the compressed signal in response to a twelfth signal from the processor.

15. The video integrated circuit as claimed in claim 14, wherein the encryption unit is one of a data encryption standard (DES) unit and a triple data encryption standard (3DES) unit.

16. The video integrated circuit as claimed in claim 1, wherein the codec performs the compression in one of an H.264 format, an MPEG-4 format, and a JPEG format.

17. The video integrated circuit as claimed in claim 1, further comprising an advanced high performance bus (AHB) for transmitting the signals of the processor and the processing signal.

19. The video processing apparatus as claimed in claim 18, wherein the first video integrated circuit is the video integrated circuit claimed in claim 1.

20. The video processing apparatus as claimed in claim 18, wherein the second video integrated circuit is the video integrated circuit claimed in claim 1.

18. A video processing apparatus connected to a video display apparatus, the video processing apparatus comprising a first video integrated circuit and a second integrated circuit, each of the first video integrated circuit and the second integrated circuit comprising:

a processor;

a video capture unit, comprising a first input end and a second input end, for receiving a digital video signal via the first input end and generating a processing signal in response to a first signal from the processor;

a watermark generation unit for receiving the processing signal and embedding a watermark into an image corresponding to the processing signal to generate an integrated signal in response to a second signal from the processor;

a codec for receiving and compressing the integrated signal to generate a compressed signal in response to a third signal from the processor; and

a video output unit, comprising a first output end and a second output end, for outputting the compressed signal to the video display apparatus via the first output end in response to a fourth signal from the processor;

wherein the second output end of the video output unit of the first integrated circuit is connected to the second input end of the video capture unit of the second integrated circuit, and the compressed signal of the first video integrated circuit is transmitted to the second video integrated circuit.