Generation of a Frame Synchronized Clock for a Wireless Video Receiver
First Claim
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1. A wireless receiver for reception of video frames having a frame rate, comprising:
- means for receiving data over a wireless link;
means for generating a frame synchronization signal; and
means for generating a video rate frequency that is synchronized to said frame synchronization signal.
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Abstract
An apparatus for receiving essentially uncompressed HDTV video must generate an accurate pixel-rate clock to enable the reconstruction of a video frame. The clock pixel-rate generated must match a received video pixel-rate. In such system, signals for generation of horizontal and vertical synchronization are not transmitted over the wireless link to conserve the use of bandwidth. In the invention, a start of frame (SOF) indication is extracted by a symbol detection and synchronization (SDS) module and is used to generate the pixel-rate clock.
23 Citations
33 Claims
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1. A wireless receiver for reception of video frames having a frame rate, comprising:
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means for receiving data over a wireless link; means for generating a frame synchronization signal; and means for generating a video rate frequency that is synchronized to said frame synchronization signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for generating a video clock that is synchronized to a frame synchronization clock of video frames having a frame rate, wherein said video frames are received over a wireless link, the method comprising the steps of:
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receiving data over said wireless link; generating said frame synchronization signal; and generating a video rate frequency that is synchronized to said frame synchronization signal. - View Dependent Claims (10, 11, 12, 13)
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14. An apparatus for generating a pixel clock for a wireless video receiver, comprising:
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an offset register; a counter; an adder, coupled to said counter and said offset register, for updating a counter current value by an offset value from said offset register; and a phased-locked loop (PLL), coupled to a clock output of said counter, for generating a pixel clock at a rate that is N times the rate of a clock provided by said counter; wherein horizontal synchronization information is received over a wireless transmission. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A pixel clock generator for a wireless video receiver, comprising:
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storage means for storing an offset value; counter means for counting clock cycles; adding means, coupled to said counter means and said storage means, for updating a current value of said counter means by an offset value stored in said storage means; and a phased-locked loop (PLL), coupled to a clock output of said counter means, for generating a pixel clock at a rate that is N times the rate of a clock provided by said counter means; wherein said pixel clock generator receives horizontal synchronization information over a wireless transmission medium. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. A method for generating a pixel clock, comprising the steps of:
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determining integer values of M and N, wherein multiplication of M by N is equal to a number of pixels in a video frame; determining a value of L, where L is derived by dividing a system frequency by a number of frames per second; determining an offset value that is equal to twice a value of M divided by L; loading said offset value in to an offset register; generating a clock that is offset by a value in said offset register;
generating M clocks between two consecutive start-of-frame (SOF) indications; andfeeding said clock to a phase-locked loop (PLL) to generate a pixel clock at a rate that is N times that of said clock; wherein an indication of SOF is derived from horizontal synchronization information received over a wireless transmission medium. - View Dependent Claims (31, 32, 33)
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Specification