Semiconductor memory device

• US 20080055958A1
• Filed: 10/25/2007
• Published: 03/06/2008
• Est. Priority Date: 05/25/2004
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Hitachi, Ltd., Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: KAJIGAYA, Kazuhiko, HANZAWA, Satoru, AKIYAMA, Satoru, SEKIGUCHI, Tomonori, TAKEMURA, Riichiro
• Granted Patent: US 7,505,299 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

Claims

1. A semiconductor memory device comprising:

a first bit line extending in a first direction;

an address buffer; and

a plurality of first memory cells each including first and second transistors disposed in the first direction and a first capacitor element connected to a first node shared with the first and second transistors, a second node of the first transistor and a second node of the second transistor being connected to the first bit line independently,

wherein at least one of the plurality of memory cell is selected according to a row address and a column address that are inputted to the address buffer simultaneously.

2. The semiconductor memory device according to claim 1, further comprising:

a plurality of first word lines extending in a second direction across the first direction and each connected to a corresponding gate of the first transistor; and

a plurality of second word lines extending in the second direction and each connected to a corresponding gate of the second transistor.

3. The semiconductor memory device according to claim 2,

wherein the first word line and the second word line are simultaneously activated.

4. The semiconductor memory device according to claim 1, further comprising:

a second bit line extending in the first direction;

a first sense amplifier connected between the first bit line and the second bit line; and

a plurality of second memory cells each including third and fourth transistors disposed in the first direction and a second capacitor element connected to a third node shared with the third and fourth transistors, a fourth node of the third transistor and a fourth node of the fourth transistor being connected to the second bit line independently;

5. The semiconductor memory device according to claim 4, further comprising:

a plurality of first word lines extending in a second direction across the first direction and each connected to a corresponding gate of the first transistor and a corresponding gate of the third transistor; and

a plurality of second word lines extending in the second direction and each connected to a corresponding gate of the second transistor and a corresponding gate of the fourth transistor.

6. The semiconductor memory device according to claim 1, further comprising:

a plurality of bit lines including the first bit line and extending in the first direction;

a plurality of cross-couple circuit each connected between corresponding two of the plurality of bit lines;

a plurality of sense amplifier drivers each including a transistor whose source-drain path is connected between a first potential and a common source node of corresponding one of the plurality of cross-couple circuits; and

a plurality of write gates each connected to corresponding two of the plurality of bit lines,

wherein the transistors of the plurality of sense amplifier drivers are off status when at least one of the plurality of write gates starts to supply a write data to corresponding bit lines.

7. The semiconductor memory device according to claim 1, further comprising:

a second bit line extending in the first direction;

a plurality of second memory cells each including third and fourth transistors disposed in the first direction and a second capacitor element connected to a third node shared with the third and fourth transistors, a fourth node of the third transistor and a fourth node of the fourth transistor being connected to the second bit line independently;

a differential amplifier including a fifth transistor whose gate is connected to the first bit line and a sixth transistor whose gate is connected to the second bit line;

8. A semiconductor memory device comprising:

a first bit line extending in a first direction;

an address buffer; and

a plurality of first memory cells each including first and second transistors disposed in the first direction and a first capacitor element connected to a first node shared with the first and second transistors, a second node of the first transistor and a second node of the second transistor being connected to the first bit line independently,

wherein at least one of the plurality of memory cell is selected according to a row address and a column address that are inputted to the address buffer sequentially.

9. The semiconductor memory device according to claim 8, further comprising:

a plurality of first word lines extending in a second direction across the first direction and each connected to a corresponding gate of the first transistor; and

a plurality of second word lines extending in the second direction and each connected to a corresponding gate of the second transistor.

10. The semiconductor memory device according to claim 9,

wherein the first word line and the second word line are simultaneously activated.

11. The semiconductor memory device according to claim 8, further comprising:

a second bit line extending in the first direction;

a first sense amplifier connected between the first bit line and the second bit line; and

a plurality of second memory cells each including third and fourth transistors disposed in the first direction and a second capacitor element connected to a third node shared with the third and fourth transistors, a fourth node of the third transistor and a fourth node of the fourth transistor being connected to the second bit line independently;

12. The semiconductor memory device according to claim 11, further comprising:

a plurality of first word lines extending in a second direction across the first direction and each connected to a corresponding gate of the first transistor and a corresponding gate of the third transistor; and

a plurality of second word lines extending in the second direction and each connected to a corresponding gate of the second transistor and a corresponding gate of the fourth transistor.

13. The semiconductor memory device according to claim 8, further comprising:

wherein the address buffer has a first address buffer inputted the row address and a second address buffer inputted the column address.