NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20080055985A1
• Filed: 09/04/2007
• Published: 03/06/2008
• Est. Priority Date: 09/04/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KANDA, Kazushige
• Granted Patent: US 7,539,053 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array including a plurality of memory cells having two or more storage states, one of the plurality of memory cells being connected to a corresponding word line of the plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction.

Claims

1. A non-volatile semiconductor memory device comprising:

a plurality of word lines;

a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines; and

a memory cell array including a plurality of memory cells having two or more storage states, one of said plurality of memory cells being connected to a corresponding word line of said plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction.

2. The non-volatile semiconductor memory device according to claim 1, wherein it is possible to change the number of storage states of said plurality of memory cells by an external input so that all of said plurality of memory cells have the same number of storage states.

3. The non-volatile semiconductor memory device according to claim 1, wherein the number of storage states of said memory cells is memorized in a fuse and it is possible to change the number of storage states of said plurality of memory cells so that all of said plurality of memory cells have the same number of storage states based on data memorized in said fuse.

4. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is a NAND type flash memory.

5. The non-volatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cells includes two transistors.

6. The non-volatile semiconductor memory device according to claim 1 wherein, the number of storage states have a first number of storage states, a second number of storage states and a third number of storage states, said first number of storage states has the lowest number of storage states, said third number of storage states has the largest number of storage states, and said second number of storage states has a number of storage states between said first number of storage states and said third number of storage states, and the number of storage states of said memory cells which are connected to said odd numbered bit lines of said plurality of bit lines and said odd numbered word lines of said plurality of word lines and said memory cells which are connected to said even numbered bit lines of said plurality of bit lines and said even numbered word lines of said plurality of word lines are set as said first number storage states.

7. The non-volatile semiconductor device according to claim 1, wherein the number of storage states of said memory cells are the same every other said word line and the same every other said bit line.

8. The non-volatile semiconductor device according to claim 1, wherein said plurality of memory cells are programmed in each of said plurality of word lines every said even numbered bit line and every said odd numbered bit line, and the voltage of said bit lines which have not been selected of said plurality of bit lines at the time of programming is controlled to a predetermined voltage.

9. A non-volatile semiconductor device comprising:

a plurality of word lines;

a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines;

a memory cell array including a plurality of memory cells having two or more storage states, said plurality of memory cells having a first address and a second address, said second address being allocated and being the same between two said adjacent memory cells, one of said plurality of memory cells being connected to a corresponding word line of said plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction; and

a plurality of sense amplifiers connected to said plurality of bit lines, said sense amplifiers amplify and output a signal which is read from said plurality of memory cells, latches data which is input or output and converts said data based on said second address into a signal.

10. The non-volatile semiconductor memory device according to claim 9, wherein it is possible to change the number of storage states of said plurality of memory cells by an external input so that all of said plurality of memory cells have the same number of storage states.

11. The non-volatile semiconductor memory device according to claim 9, wherein the number of storage states of said memory cells is memorized in a fuse and it is possible to change the number of storage states of said plurality of memory cells so that all of said plurality of memory cells have the same number of storage states based on data memorized in said fuse.

12. The non-volatile semiconductor memory device according to claim 9, wherein the non-volatile semiconductor memory device is a NAND type flash memory.

13. The non-volatile semiconductor memory device according to claim 9, wherein each of said plurality of memory cells includes two transistors.

14. The non-volatile semiconductor memory device according to claim 9, wherein the number of storage states have a first number of storage states, a second number of storage states, a third number of storage states and a fourth number of storage states, said first number of storage states being lower than said second number of storage states which is lower than said third number of storage states which is lower than said fourth number of storage states, said first number of storage states and said third number of storage states are set as the number of storage states which are stored in said memory cells which are connected to the same word line, and said second number of storage states and said fourth number of storage states are set as the number of storage states which are stored in said memory cells which are connected to the same word line adjacent to said word line, and the order of selecting said odd numbered bit lines and said even numbered bit lines is reversed every said adjacent word line.

15. The non-volatile semiconductor memory device according to claim 9, wherein said plurality of memory cells are selected in each of said plurality of word lines every said even numbered bit line and every said odd numbered bit line based on said second address, and the voltage of said bit lines which have not been selected of said plurality of bit lines at the time of programming is controlled to a predetermined voltage.

16. A non-volatile semiconductor device comprising:

a plurality of word lines;

a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines;

a memory cell array including a plurality of memory cells having two or more storage states, said plurality of memory cells having a first address, a second address and a third address, said second address being allocated and being the same between two said consecutive memory cells among three consecutive memory cells which are adjacent and said third address which is allocated to another memory cell among said three memory cells, one of said plurality of memory cells being connected to a corresponding word line of said plurality of word lines, the number of storage states of said memory cell among three consecutive memory cells which are adjacent is different; and

a plurality of sense amplifiers connected to said plurality of bit lines, said sense amplifiers amplify and output a signal which is read from said plurality of memory cells, latches data which is input or output and converts said data based on said second address and said third address into a signal.

17. The non-volatile semiconductor memory device according to claim 16, wherein it is possible to change the number of storage states of said plurality of memory cells by an external input so that all of said plurality of memory cells have the same number of storage states.

18. The non-volatile semiconductor memory device according to claim 16, wherein the number of storage states of said memory cells is memorized in a fuse and it is possible to change the number of storage states of said plurality of memory cells so that all of said plurality of memory cells have the same number of storage states based on data memorized in said fuse.

19. The non-volatile semiconductor memory device according to claim 16, wherein the non-volatile semiconductor memory device is a NAND type flash memory.

20. The non-volatile semiconductor memory device according to claim 16, wherein each of said plurality of memory cells includes two transistors.

21. The non-volatile semiconductor memory device according to claim 16, wherein the number of storage states of said memory cells are the same in the memory cells which are allocated with a common second address.

22. The non-volatile semiconductor memory device according to claim 16, wherein the number of storage states of said memory cells are different in the memory cells which are allocated with a common second address.

23. The non-volatile semiconductor memory device according to claim 16, wherein said plurality of memory cells are selected in each of said plurality of word lines every said even numbered bit line and every said odd numbered bit line based on said second address and said third address, and the voltage of said bit lines which have not been selected of said plurality of bit lines at the time of programming is controlled to a predetermined voltage.