Semiconductor memory

• US 20080056031A1
• Filed: 10/12/2007
• Published: 03/06/2008
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takahashi, Hiroyuki, Nakagawa, Atsushi, Hirota, Takuya
• Granted Patent: US 7,663,945 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Claims

1. A semiconductor device comprising a delay circuit, the delay circuit comprising:

at least one circuit unit comprising;

an inverter including;

a first MOS transistor having a source thereof connected to a first power supply; and

a second MOS transistor having a source thereof connected to a second power supply, having a gate thereof connected in common with a gate of said first MOS transistor to an input terminal, and having a drain thereof connected in common with a drain of said first MOS transistor to an output terminal, said second MOS transistor having a different conductivity type from a conductivity type of said first MOS transistor;

a resistor having one terminal thereof connected to said output terminal of said inverter; and

a MOS capacitor connected between the other terminal of said resistor and said first or second power supply,

the delay circuit having a characteristic in which a delay time thereof decreases more when a provided power supply voltage is low than when the provided power supply voltage is high.

2. A semiconductor device comprising:

a delay circuit for delaying an input signal and outputting a so delayed signal; and

a circuit for outputting a result of a predetermined logic operation on the input signal and an output signal of said delay circuit;

wherein the delay circuit comprises;

at least one circuit unit comprising;

an inverter including;

a first MOS transistor having a source thereof connected to a first power supply; and

a second MOS transistor having a source thereof connected to a second power supply, having a gate thereof connected in common with a gate of said first MOS transistor to an input terminal, and having a drain thereof connected in common with a drain of said first MOS transistor to an output terminal, said second MOS transistor having a different conductivity type from a conductivity type of said first MOS transistor;

a resistor having one terminal thereof connected to said output terminal of said inverter; and

a MOS capacitor connected between the other terminal of said resistor and said first or second power supply.

3. A memory device, comprising:

a memory cell array including a plurality of memory cells;

a driver for driving a word line coupled to the selected memory cell;

a first control circuit for generating a control signal to control said driver; and

a sense amplifier for amplifying a voltage on a bit line coupled to the selected memory cell;

wherein said first control circuit has a first delay characteristic in which the higher a power supply voltage applied to the first control circuit becomes, the larger a delay time of the first control circuit becomes, while said sense amplifier has a second delay characteristic in which the higher a power supply voltage applied to said sense amplifier becomes, the smaller a delay time of the circuit becomes.

4. A memory device, comprising:

a memory cell array including a plurality of memory cells; and

a first control circuit for accessing a selected memory cell;

said first control circuit having a first delay characteristic in which the higher a power supply voltage applied to the first control circuit becomes, the larger a delay time of the first control circuit becomes.

5. The memory device according to claim 4, further comprising

a second control circuit for accessing the selected memory cell;

said second control circuit having a second delay characteristic in which the higher a power supply voltage applied to the second control circuit becomes, the smaller a delay time of the second control circuit becomes.