Methods and apparatus to provide refresh for global out of range read requests

• US 20080056043A1
• Filed: 08/30/2006
• Published: 03/06/2008
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jahnke, Steve Richard, Hamakawa, Hiromichi
• Granted Patent: US 7,508,728 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Abstract

Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

Claims

1. A method of providing a refresh signal to a memory cell, comprising:

receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line;

coupling a memory driver logic device to the memory cell;

coupling an out of range logic decoder to provide a fixed logic input to a first input of the memory driver logic device; and

providing address logic to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

2. The method of claim 1, wherein the memory address is a column address and the memory cell is one of a row of memory cells.

3. The method of claim 1, wherein the memory driver logic device is an AND gate.

4. The method of claim 1, wherein the address logic includes four AND gates, one of the four AND gates is to produce a high signal when one of the four values associated with the two least significant bits of the address is entered.

5. The method of claim 1, wherein the out of range logic decoder includes a high voltage input or an address decoder coupled to the most significant address line.

6. A method of providing a refresh signal to one of a plurality of memory cells, comprising:

receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line;

coupling memory driver logic devices to each of a respective one of the plurality of memory cells;

coupling an out of range logic decoder to provide a fixed logic input to a first input of the memory driver logic devices associated with the memory cells having an address with the same least significant bits as any one of a plurality of out of range addresses; and

providing address decoder logic to activate the memory driver logic devices to send a read enable signal to a memory cell, if the address is one of the out of range addresses.

7. The method of claim 6, wherein the memory address is a column address and the memory cell is one of a row of eight memory cells.

8. The method of claim 6, wherein the memory driver logic device is an AND gate.

9. The method of claim 6, wherein the address logic includes four AND gates, one of the four AND gates is to produce a high signal when one of the four values associated with the two least significant bits of the address is entered.

10. The method of claim 6, wherein the out of range logic decoder includes a high voltage input or an address decoder coupled to the most significant address line.

11. An address decoder to provide a refresh signal to a memory cell having an address having the same least significant bits as at least one out of range address, comprising:

a memory address input including address lines ranging from a most significant bit address line to a least significant bit address line;

an address line logic device having an input coupled to the address lines and an output;

a memory driver logic device having a first input coupled to the output of the address line logic device and an output coupled to the memory cell; and

an out of range logic decoder to provide a fixed logic input to a first input of the memory driver logic device, wherein the address line logic device and the out of range logic decoder are to cause the memory driver logic device to send a read enable signal to the memory cell if a memory address received on the address input is an out of range address.

12. The address decoder of claim 11, wherein the memory address is a column address and the memory cell is one of a row of memory cells.

13. The address decoder of claim 11, wherein the memory driver logic device is an AND gate.

14. The address decoder of claim 11, wherein the address line logic device includes four AND gates, one of the four AND gates producing a high signal when one of the four values of the least significant bits of the address is entered.

15. The address decoder of claim 11, wherein the out of range logic decoder includes a high voltage input or an address decoder coupled to the most significant address line.

16. A column address decoder to address one of a plurality of memory blocks in a memory array, each of the memory blocks having up to a four bit address, the column address decoder comprising:

a column address input including two least significant bit column address lines, a third least significant bit column address line, and a most significant bit column address line;

a plurality of block driver logic devices, each coupled to one of the plurality of memory blocks, the block driver logic devices to produce a select signal to refresh the memory block;

a first logic decoder coupled to the two least significant column address lines, the first logic decoder producing four outputs each corresponding to one of the four values of the two least significant column address lines;

a second logic decoder coupled to the third least significant and the most significant bit column address lines, the second logic decoder producing four outputs each corresponding to one of the four values of the third least significant and the most significant bit column address lines; and

wherein the outputs of the first and second logic decoders are connectable to the plurality of block driver logic devices to produce the select signal from one of the plurality of block driver logic devices based on an up to four bit address received on the column address input.

17. The column address decoder of claim 16, wherein the memory blocks have a two bit address and the block driver logic devices are AND gates having a first input coupled to the first logic decoder and a second input coupled to the second logic decoder to produce the select signal from one of the block driver logic devices when an out of range address is received having the same least significant bit as the two bit address of the memory block corresponding to one of the block driver logic devices.

18. The column address decoder of claim 16 further comprising an out of range control line connectable to the plurality of block driver logic devices to produce a select signal on one of the plurality of block driver logic devices when an out of range address is received on the column address input.

19. The column address decoder of claim 18, wherein the memory blocks have three bit addresses, the memory array having one to three possible out of range addresses and the out of range control line is connected to the block driver logic devices corresponding to memory blocks with an address having the same two least significant bits as the possible out of range addresses, wherein the out of range control line is coupled to a high logic input, and the out of range control line in conjunction with one of the first decoder logic outputs is to activate one of block driver logic devices to produce a select signal on the memory block with an address having the same two least significant bits of a received out of range address.

20. The column address decoder of claim 18, wherein the memory blocks have four bit addresses, the memory array has four to seven possible out of range addresses, and wherein the out of range control line is connected to the block driver logic devices coupled to the memory blocks having an address with a logical zero as a third least significant bit and the same two least significant bits as one of the possible out of range addresses, wherein the out of range control line is coupled to an inverted third least significant bit address column line, and wherein the output of the second decoder corresponding to a logical one as the third least significant bit is coupled to the block driver logic devices coupled to the memory blocks having an address having a logical one as the third least significant bit and the same two least significant bits as one of the possible out of range addresses, and wherein the out of range control line or the second decoder in conjunction with the first decoder logic output activates one of block driver logic devices to produce a select signal on the memory block with an address having the same three least significant bits of a received out of range address.

21. The column address decoder of claim 18, wherein the memory blocks have four bit addresses, the memory array has one to three possible out of range addresses and the out of range control line is connected to the block driver logic devices corresponding to memory blocks with addresses having the same three least significant bits as the possible out of range addresses, wherein the out of range control line is coupled to the third least significant bit address column line, the out of range control line in conjunction with one of the first decoder logic outputs is to activate one of block driver logic devices to produce a select signal on the memory block with an address having the same three least significant bits of a received out of range address.

22. The column address decoder of claim 16, wherein the block driver logic devices are AND gates.

23. The column address decoder of claim 16, wherein the first and second decoder include four AND gates, one of the four AND gates to produce a high signal when one of the four values of the two bit addresses is entered.

24. The column address decoder of claim 16 wherein, the memory blocks each include eight rows of memory cells.

25. A method of configuring a column address decoder to refresh one of a plurality of memory blocks, each having a four bit address, in a memory array, on receiving a global out of range address, the method comprising:

determining the number of memory blocks;

coupling a block driver logic device with a column select line to one of the memory blocks;

providing a first decoder coupled to two least significant address bit inputs of a four bit address input to generate one of four outputs each corresponding to one of the four values of the two least significant address bit inputs;

providing a second decoder coupled to a third least significant address bit input of the four bit address input and a most significant address bit input of the four bit address input to generate an output signal one of four outputs each corresponding to one of the four values of the third least significant address bit and most significant bit inputs;

providing an out of range control line; and

activating the logic block device to provide a refresh signal on the column select line via two of the first and second decoder and the out of range control line to the corresponding memory block when a global out of range address having the same least three significant bits of the memory block address is received on the address input.

26. The method of claim 25, wherein the column address decoder is a programmable logic array.

27. The method of claim 25, wherein the most significant bit and the third least significant bit of the address inputs are logical zeros, the memory array has three memory blocks, and wherein the memory block with the address having the same least significant bit as a global out of range address is activated by the first and second decoder.

28. The method of claim 25 further comprising:

coupling the out of range control line to a high logical input; and

wherein the most significant bit of the address input is a logical zero, the memory array has up to seven memory blocks, and wherein the block driver logic device is activated by one of the four outputs of the first decoder and the out of range control line.

29. The method of claim 25 further comprising:

coupling the out of range control line to an inverted third least significant bit line; and

wherein the memory array has between nine and fifteen memory blocks and wherein the block driver logic device is activated by one of the four outputs of the first decoder and the out of range control line when the received out of range address has a logical zero value in the third least significant address bit or the block driver logic device is activated by one of the four outputs of the first decoder and one of the four outputs of the second decoder when the received out of range address has a logical one value in the third least significant address bit.

30. The method of claim 25 further comprising:

coupling the out of range control line to the third least significant bit address input; and

wherein the memory array has between twelve and fifteen memory blocks and wherein the block driver logic device is activated by one of the four outputs of the first decoder and the out of range control line.

31. The method of claim 25, wherein the memory blocks each include eight rows of memory cells.

32. A column address decoder to provide a refresh signal to one of three memory blocks having a two bit address in a memory array, on receiving a global out of range two bit address from a possible range of four addresses, the column address decoder comprising:

a least significant and most significant column address input line to accept a two bit address input;

a block driver logic device having a first and second input and an output coupled to one of memory blocks, the block driver logic device activated by the first and second inputs to produce a select signal to refresh the memory block having the same least significant bit address as the global out of range two bit address;

an out of range control line having a first activation signal coupled to the first input of the block driver logic device;

decode logic having inputs coupled to the column address lines and outputs coupled to the first input of the block driver logic device, the decode logic sending a second activation signal to the second input of the block driver logic device on receiving the global out of range address on the two bit address input.

33. The column address decoder of claim 32, wherein the block driver logic device is an AND gate and the first and second activation signals are logical high signals.

34. A column address decoder to provide a refresh signal to one of a plurality memory blocks each having a three bit address in a memory array, on receiving a global out of range three bit address from a possible three addresses, the column address decoder comprising:

a most significant bit column address input line and two least significant bit column address lines to accept a three bit column address input;

a plurality of block driver logic devices each having two inputs and an output, each coupled to one of the plurality of memory blocks, the block driver logic devices to produce a select signal to refresh the memory block;

a first logic decoder coupled to the two least significant column address lines, the first logic decoder producing four outputs providing a first activation signal, each of the four outputs corresponding to each of the four values of the two least significant column address lines, one of the four outputs being coupled to the first input of each of the plurality of block driver logic devices; and

a global out of range control line to provide an activation signal to the second input of each of the plurality of block driver logic devices coupled to memory blocks with an address having the same two least significant bits as each of the possible global out of range addresses.

35. The column address decoder of claim 34, wherein the block driver logic devices are AND gates and the first and second activation signals are logical high signals.

36. A column address decoder to provide a refresh signal to one of a plurality of up to fifteen memory blocks each having a four bit address in a memory array, on receiving a global out of range four bit address from a possible seven global out of range addresses, the column address decoder comprising:

four column address input lines including two least significant bit column address lines, a third least significant bit column address line and a most significant bit column address line, the column address input lines to receive a four bit address input;

a plurality of block driver logic devices each having two inputs and an output, each coupled to one of the plurality of memory blocks, the block driver logic devices to produce a select signal to refresh one of the plurality of memory blocks;

a first logic decoder coupled to the two least significant column address lines, the first logic decoder producing four outputs providing a first activation signal, each of the four outputs corresponding to each of the four values of the two least significant column address lines, one of the four outputs being coupled to the first input of each of the plurality of block driver logic devices;

a global out of range decoder to provide an activation signal to the second input of each of the plurality of block driver logic devices coupled to memory blocks with an address having the same three least significant bits as each of the possible global out of range addresses; and

wherein the decode logic sends a second activation signal to the second input of the block driver logic devices coupled to the memory block with an address having the same three least significant bits as a received the global out of range address on the four bit address input to activate the block driver logic device to refresh the memory block.

37. The column address decoder of claim 36, wherein the global out of range decoder includes an out of range control line coupled to an inverted third least significant bit address input line to output an activation signal when the third least significant bit of the input address is a logical one, and wherein the second input of each of the plurality of block driver logic devices is coupled to memory blocks with and address having the same three least significant bits as each of the possible global out of range addresses are coupled to either the out of range control line or the logic decoder;

and wherein the memory array has between four and seven out of range four bit addresses.

38. The column address decoder of claim 36, wherein the global out of range decoder includes an out of range control line, the out of range control line outputting the value of the third least significant bit address input line and coupled to the second input of each of the plurality of block driver logic devices coupled to memory blocks with an address having the same three least significant bits as each of the possible global out of range addresses;

and wherein the memory array has between one and three out of range four bit addresses.

39. The column address decoder of claim 36, wherein the block driver logic devices are AND gates and the first and second activation signals are logical high signals.

40. A method of providing a refresh signal to a memory cell with an address associated with an out of range address, comprising:

receiving an address on address lines ranging from a most significant bit address line to a least significant bit address line;

coupling a memory driver logic device to the memory cell;

coupling an out of range logic decoder to provide a fixed logic input to a first input of the memory driver logic device; and

providing address logic to cause the memory driver logic device to send an enable sign to the memory cell if the address is the local out of range address.

41. A method of providing a refresh signal to one of a plurality of memory cells each having a unique address including a most significant bit and least significant bit or bits, comprising:

receiving an address on address lines ranging from a most significant bit address line to a least significant bit address line;

coupling row driver logic devices for a respective one of the plurality of memory cells;

coupling an out of range logic decoder to provide a fixed logic input to a first input of memory driver logic devices associated with the memory cells having an address with the same least significant bits as any one of possible out of range addresses; and

providing address decoder logic to activate the memory driver to send a read enable signal to the respective memory cell, if the address is one of the possible out of range addresses.

42. An address decoder to provide a refresh signal to a memory cell having an address having the same least significant bits as at least one out of range address, comprising:

an address input including address lines ranging from a most significant bit address line to a least significant bit address line;

an address line logic device having an input coupled to the address lines and an output;

a memory driver logic device having a first input coupled to the output of the address line logic device and an output coupled to the memory cell;

an out of range logic decoder to provide a fixed logic input to a first input of the memory driver logic device, wherein the address line logic device and the out of range logic decoder cause the memory driver logic device to send a read enable signal to the memory cell if an address received on the address input is an out of range address.