Transmitter and receiver using forward clock overlaying link information
First Claim
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1. A transceiver, comprising:
- a clock signal line;
data signal lines;
a transmitter that transmits a clock signal and data signals by the aid of the clock signal line and the data signal lines; and
a receiver that receives the clock signal and the data signals which are transmitted from the transmitter by the aid of the clock signal line and the data signal lines,wherein the transmitter includes a encoder circuit that transmits a bit sequence obtained by encoding link information to the clock signal line, andwherein the receiver includes an extractor circuit that extracts a clock component from the signal that is received from the clock signal line, a decoder circuit that decodes the extracted signal to reproduce the link information, and a deskew circuit that adjusts a skew that is lower than one bit on the basis of the clock component.
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Abstract
A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
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Citations
18 Claims
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1. A transceiver, comprising:
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a clock signal line; data signal lines; a transmitter that transmits a clock signal and data signals by the aid of the clock signal line and the data signal lines; and a receiver that receives the clock signal and the data signals which are transmitted from the transmitter by the aid of the clock signal line and the data signal lines, wherein the transmitter includes a encoder circuit that transmits a bit sequence obtained by encoding link information to the clock signal line, and wherein the receiver includes an extractor circuit that extracts a clock component from the signal that is received from the clock signal line, a decoder circuit that decodes the extracted signal to reproduce the link information, and a deskew circuit that adjusts a skew that is lower than one bit on the basis of the clock component. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A transmitter that transmits a clock signal and data signals by the aid of a clock signal line and data signal lines, the transmitter comprising:
an encoder circuit that transmits a bit sequence obtained by encoding link information to the clock signal line. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A receiver that receives a clock signal and data signals which are transmitted from a transmitter by the aid of a clock signal line and data signal lines, the receiver comprising:
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an extractor circuit that extracts a clock component from a signal that is received from the clock signal line; a decoder circuit that decodes the extracted signal to reproduce link information; and an adjuster circuit that adjust a skew that is lower than one bit on the basis of the clock component. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsYamashita, Hiroki, Saito, Tatsuya, Chujo, Norio, Toyoda, Hidehiro
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current375/219
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CPC Class CodesH04L 7/0337 Selecting between two or mo...
