Decoding apparatus and decoding method

• US 20080056401A1
• Filed: 07/20/2007
• Published: 03/06/2008
• Est. Priority Date: 07/27/2006
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamagishi, Hiroyuki, Kondou, Keitarou
• Granted Patent: US 7,860,181 B2
• Time in Patent Office: Days
• US Class Current: 375/265
• CPC Class Codes: H04L 25/03197 methods of calculation involving metrics
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343

Abstract

Disclosed herein is a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing the coding constraint is greater than the length of a channel memory of the partial response. The apparatus may include a first calculation unit configured to carry out a first calculation on first branch information, which may be defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for the first branches; and a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of the first calculation.

Claims

1. A decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing said coding constraint is greater than the length of a channel memory of said partial response, said decoding apparatus comprising:

a first calculation unit configured to carry out a first calculation on first branch information, which is defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for said first branches; and

a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of said first calculation.

2. The decoding apparatus according to claim 1, said decoding apparatus further comprising

a third calculation unit configured to carry out said second calculation on second path information defined as information on second paths for second branches included in said three or more branches merging in said state determined in advance as branches having the same branch information, wherein:

said first branch information includes second branch information, which is defined as information on said second branches, and third branch information defined as information on third branches included in said branches merging in said state determined in advance as branches other than said second branches;

said first path information includes a third calculation value obtained as a result of said second calculation carried out by said third calculation unit and third path information defined as information on third paths for said third branches;

said first calculation unit carries out said first calculation on said first branch information and said third calculation value as well as said third branch information and said third path information; and

said third calculation unit carries out said second calculation prior to a predetermined time of processing carried out by said first and a second calculation units.

3. The decoding apparatus according to claim 1 wherein said first branches are defined as branches merging in each of states obtained as a result of splitting a predetermined state in which three or more branches merge so that the number of aforementioned first branches merging in each of said states obtained as a result of splitting said predetermined state is smaller than the number of branches merging in said predetermined state.

4. The decoding apparatus according to claim 1, said decoding apparatus capable of decoding channel input bits by adoption of a Viterbi algorithm, a BCJR (Bahl, Cocke, Jelineck and Raviv) algorithm, a Log-MAP (Maximum A Posteriori Probability) algorithm or a Max-Log-MAP algorithm.

5. The decoding apparatus according to claim 1, said decoding apparatus capable of decoding channel input bits for every time instant, wherein said first calculation unit carries out said first calculation at a time instant immediately preceding calculations carried out by said second to fourth calculation units.

6. The decoding apparatus according to claim 1, said decoding apparatus capable of decoding channel input bits for every plurality of time instants, wherein said first calculation unit carries out said first calculation at a time instant preceding calculations carried out by said second to fourth calculation units by a plurality of time instants.

7. A decoding method to be adopted in a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing said coding constraint is greater than the length of a channel memory of said partial response, said decoding method comprising:

carrying out a first calculation on first branch information, which is defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for said first branches; and

carrying out a second calculation on a first calculation value obtained as a result of said first calculation.