METHOD FOR PATTERNING CONTACT ETCH STOP LAYERS BY USING A PLANARIZATION PROCESS

• US 20080057720A1
• Filed: 03/28/2007
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Frohberg, Kai, Mueller, Sven, Schwan, Christoph
• Granted Patent: US 7,838,354 B2
• Time in Patent Office: Days
• US Class Current: 438/699
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization
• CPC Class Codes: Y10S 438/958 Passivation layer
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.

Claims

1. A method, comprising:

forming a first stress-inducing layer above a first device region and a second device region, said first stress-inducing layer having an intrinsic stress of approximately 1.5 Giga Pascal or higher;

forming a first planarization layer above said first and second device regions to planarize a surface topography of said first and second device regions;

forming a first resist mask above said first planarization layer to cover said first device region; and

removing an exposed portion of said first planarization layer and said first stress-inducing layer from said second device region.

2. The method of claim 1, wherein forming said first planarization layer comprises forming a layer of polymer material in a highly deformable state so as to establish topography changes in said first and second device regions.

3. The method of claim 1, wherein said first planarization layer is formed to have anti-reflective characteristics with respect to an exposure radiation used to form said first resist mask.

4. The method of claim 1, further comprising removing said first planarization layer and said first resist mask from said first device region and forming an etch control layer followed by forming a second stress-inducing layer above said first and second device regions.

5. The method of claim 4, further comprising forming a second planarization layer and forming a second resist mask above said second planarization layer.

6. The method of claim 5, further comprising removing a portion of said second stress-inducing layer located above said first device region on the basis of said second resist mask.

7. The method of claim 1, wherein said first stress-inducing layer is formed by a non-conformal deposition technique.

8. The method of claim 4 wherein said second stress-inducing layer is formed by a non-conformal deposition technique.

9. The method of claim 1, wherein forming said planarization layer comprises depositing said planarization layer and performing a planarization process.

10. A method, comprising:

forming a planarization layer above first and second transistors having formed there-above a first stress-inducing layer having a first type of intrinsic stress;

forming a resist mask on said planarization layer, said resist mask covering said first transistors;

removing said first stress-inducing layer from above said second transistors; and

forming a second stress-inducing layer above said first and second transistors, said second stress-inducing layer having a second type of intrinsic stress that differs from said first type of intrinsic stress.

11. The method of claim 10, wherein said planarization layer is comprised of an interlayer dielectric material and said second stress-inducing layer is formed on said planarization layer.

12. The method of claim 11, further comprising removing said second stress-inducing layer above said first transistors.

13. The method of claim 12, wherein said planarization layer has an intrinsic stress corresponding to said first type of stress.

14. The method of claim 13, further comprising forming a further portion of said interlayer dielectric material above said first and second transistors, said further portion of said interlayer dielectric material having said second type of intrinsic stress.

15. The method of claim 10, wherein said planarization layer comprises silicon dioxide.

16. The method of claim 10, further comprising forming an etch stop layer with respect to said first stress layer prior to forming said first contact etch stop layer.

17. The method of claim 10, wherein forming said planarization layer comprises depositing a dielectric material and performing a planarization process.

18. A method, comprising:

forming a first stress-inducing layer having a first type of intrinsic stress above a first device region and a second device region, said first and second device regions comprising first and second transistors, respectively;

forming a first interlayer dielectric material above said first and second device regions, said first interlayer dielectric material having said first type of intrinsic stress, and reducing height differences of a surface topography of said first and second device regions;

selectively removing said first stress-inducing layer and said first interlayer dielectric material from said second device region;

selectively forming a second stress-inducing layer having a second type of intrinsic stress above said second device region; and

forming a second interlayer dielectric material above said first and second device regions, said second interlayer dielectric material having said second type of intrinsic stress.

19. The method of claim 18, further comprising planarizing said first interlayer dielectric material.

20. The method of claim 18, further comprising forming a third interlayer dielectric material above said first and second device regions.