Power control for a dual mode transmitter

• US 20080057883A1
• Filed: 08/29/2006
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pan, Meng-An
• Granted Patent: US 7,860,467 B2
• Time in Patent Office: Days
• US Class Current: 455/127.1
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 2203/45052 the cascode stage of the cascode differential amplifier being controlled by a controlling signal, which controlling signal can also be the input signal
• CPC Class Codes: H03F 2203/45371 the AAC comprising parallel coupled multiple transistors at their source and gate and drain or at their base and emitter and collector, e.g. in a cascode dif amp, only those forming the composite common source transistor or the composite common emitter transistor respectively
• CPC Class Codes: H03F 2203/45396 the AAC comprising one or more switches
• CPC Class Codes: H03F 2203/45481 the CSC comprising only a direct connection to the supply voltage, no other components being present
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A circuit may be provided. The circuit may be a component of a dual mode transmitter such as a transmitter from the 802.11x family. The circuit may comprise an amplifier configured to provide amplification of a signal for transmission in either a first transmission mode or a second transmission mode, using power supplied from a power supply, the amplifier including at least one cascode transistor in series with at least one amplifying transistor. The circuit may further comprise a power controller configured to define an operating characteristic of the at least one cascode transistor, and thereby designate an amount of the power from the power supply that is used by the amplifier during the amplification, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.

Claims

1. A circuit comprising:

an amplifier configured to provide amplification of a signal for transmission in either a first transmission mode or a second transmission mode, using power supplied from a power supply, the amplifier including at least one cascode transistor in series with at least one amplifying transistor; and

a power controller configured to define an operating characteristic of the at least one cascode transistor, and thereby designate an amount of power from the power supply that is used by the amplifier during the amplification, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.

2. The circuit of claim 1 wherein the power controller is configured to cause a change in a voltage from the power supply, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.

3. The circuit of claim 2 wherein the change in the voltage from the power supply includes setting a switching regulator to adjust the voltage from the power supply.

4. The circuit of claim 1 wherein the operating characteristic includes a cascode bias level of the at least one cascode transistor.

5. The circuit of claim 4 wherein, in one of the first transmission mode and the second transmission mode, the cascode bias level is set so as to define a drain voltage of the amplifying transistor as being substantially equivalent to a normal operating voltage of the amplifying transistor.

6. The circuit of claim 4 wherein, in one of the first transmission mode and the second transmission mode, the cascode bias level is substantially equivalent to a voltage of the power supply.

7. The circuit of claim 1 wherein the power controller is configured to access a memory to determine the operating characteristic.

8. The circuit of claim 1 wherein the power controller comprises a current controller that is configured to cause a change in a current from the power supply, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.

9. The circuit of claim 8 wherein the at least one cascode transistor in series with the at least one amplifying transistor includes a number of decomposed branches, and wherein the operating characteristic of the at least one cascode transistor includes a selective activation or deactivation thereof as part of the change in the current from the power supply.

10. The circuit of claim 9 wherein the selective activation or deactivation thereof of the at least one cascode transistor to provide the change in the current from the power supply includes activating and/or deactivating at least one switch connected to the at least one cascode transistor.

11. The circuit of claim 9 wherein the current controller is configured to access a memory to obtain a number of decomposed branches to be selectively activated or deactivated, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.

12. The circuit of claim 1 wherein the at least one cascode transistor includes a thick oxide transistor.

13. A method comprising:

providing an amplifier within a multi-mode transmitter, the amplifier powered by a power supply and including at least one cascode transistor in series with at least one amplifying transistor;

providing a first power control option defining an amount of power used by the amplifier in an operational mode of the transmitter and associated with a first operating characteristic of the at least one cascode transistor; and

providing a second power control option defining an amount of power used by the amplifier in the operational mode of the transmitter and associated with a second operating characteristic of the at least one cascode transistor.

14. The method of claim 13 further comprising providing a memory configured to store information associated with the first and second operating characteristics of the at least one cascode transistor.

15. The method of claim 13 wherein the first power control option includes adjusting a voltage used by the amplifier from the power supply, and wherein the first operating characteristic includes a cascode bias level of the at least one cascode transistor that is set in conjunction with use of a switching regulator to adjust the voltage.

16. The method of claim 13 wherein the second power control option includes adjusting a current drawn from the power supply by the amplifier, and wherein the second operating characteristic includes an activation or deactivation of the at least one cascode transistor from among a plurality of decomposed parallel branches of cascode transistors.

17. A method comprising:

making a determination to operate a transmitter in a first operational mode or a second operational mode, the first operational mode requiring less power for operation of an amplifier of the transmitter than the second operational mode;

setting a bias level of a plurality of cascode transistors of the amplifier, based on the determination;

setting a voltage level of a power supply of the amplifier, based on the determination; and

designating a number of the plurality of cascode transistors to be active within the amplifier, based on the determination.

18. The method of claim 17 wherein one or more of setting the bias level, setting the voltage level, and/or designating the number of the plurality of cascode transistors to be active with the amplifier comprises:

accessing a memory in which one or more of bias levels, voltage levels, and/or numbers of the plurality of cascode transistors are stored

19. The method of claim 17 wherein the designating comprises:

enabling or disabling selected ones of a plurality of decomposed parallel branches of the plurality of cascode transistors, based on the determination.

20. The method of claim 19 wherein the enabling or disabling selected ones of the plurality of cascode transistors further comprises:

controlling a switch connected to a selected one of the plurality of cascode transistors.