FAST INTERRUPT DISABLING AND PROCESSING IN A PARALLEL COMPUTING ENVIRONMENT

• US 20080059677A1
• Filed: 08/31/2006
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blocksome, Michael Alan, Lieber, Derek, Ratterman, Joseph D., Smith, Brian Edward, Archer, Charles Jens, McCarthy, Patrick Joseph, Parker, Jeffrey John, Inglett, Todd Alan, Mundy, Michael Basil
• Application Number:
  US11/469,034
• Publication Number:
  US 20080059677A1
• Time in Patent Office: Days
• US Class Current: 710/262
• CPC Class Codes: G06F 2209/543 Local
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

Embodiments of the present invention provide techniques for protecting critical sections of code being executed in a lightweight kernel environment suited for use on a compute node of a parallel computing system. These techniques avoid the overhead associated with a full kernel mode implementation of a network layer, while also allowing network interrupts to be processed without corrupting shared memory state. In one embodiment, a system call may be used to disable interrupts upon entry to a routine configured to process an event associated with the interrupt.

Claims

1. A method for interrupt disabling and processing by a compute node running a user application in a parallel computing environment, comprising:

upon entry to a critical section of code, disabling interrupts from being delivered to the user application, wherein the critical section of code includes at least an instruction that modifies a shared memory value;

invoking, by the user application, a call configured to process an asynchronous event; and

upon exit from the critical section of code, re-enabling the delivery of interrupts.

2. The method of claim 1, wherein the critical section includes a call to a non-reentrant function.

3. The method of claim 1, wherein processing an interrupt while executing the critical section would corrupt a memory state of the shared memory value.

4. The method of claim 1, wherein an asynchronous event results in an interrupt being generated and delivered to the user application.

5. The method of claim 4, wherein the asynchronous event is the receipt of incoming network data by the compute node destined for the user application.

6. The method of claim 1, further comprising, after exiting the exit from the critical section of code, redelivering an interrupt to the user application received while the critical section of code was being executed by the compute node.

7. The method of claim 1, wherein the compute node is connected to a plurality of other compute nodes, and wherein messages may be passed to the compute node using a point-to-point torus configuration.

8. A computer-readable medium containing a program which, when executed, performs an operation for interrupt disabling and processing by a compute node running a user application in a parallel computing environment, comprising:

upon entry to a critical section of code, disabling interrupts from being delivered to the user application, wherein the critical section of code includes at least an instruction that modifies a shared memory value;

invoking, by the user application, a call configured to process an asynchronous event; and

upon exit from the critical section of code, re-enabling the delivery of interrupts.

9. The computer-readable medium of claim 8, wherein the critical section includes a call to a non-reentrant function.

10. The computer-readable medium of claim 8, wherein processing an interrupt while executing the critical section would corrupt a memory state of the shared memory value.

11. The computer-readable medium of claim 8, wherein an asynchronous event results in an interrupt being generated and delivered to the user application.

12. The computer-readable medium of claim 11, wherein the asynchronous event is the receipt of incoming network data by the compute node destined for the user application.

13. The computer-readable medium of claim 8, wherein the operation further comprises, after exiting the exit from the critical section of code, redelivering an interrupt to the user application received while the critical section of code was being executed by the compute node.

14. The computer-readable medium of claim 8, wherein the compute node is connected to a plurality of other compute nodes, and wherein messages may be passed to the compute node over a point-to-point torus configuration.

15. A system, comprising:

a compute node having at least one processor;

a memory coupled to the compute node and configured to store, a shared memory data structure and a lightweight kernel; and

a user application configured to;

upon entry to a critical section of code, disabling interrupts from being delivered to the user application, wherein the critical section of code includes at least an instruction that modifies a shared memory value;

invoke a call configured to process an asynchronous event; and

upon exit from the critical section of code, re-enable the delivery of interrupts.

16. The system of claim 15, wherein the critical section includes a call to a non-reentrant function.

17. The system of claim 15, wherein processing an interrupt while executing the critical section would corrupt a memory state of the shared memory value.

18. The system of claim 15, wherein an asynchronous event results in an interrupt being generated and delivered to the user application.

19. The system of claim 18, wherein the asynchronous event is the receipt of incoming network data by the compute node destined for the user application.

20. The system of claim 15, wherein the user application is further configured to, after exiting the exit from the critical section of code, redeliver an interrupt to the user application received while the critical section of code was being executed by the compute node.

21. The system of claim 15, wherein the compute node is connected to a plurality of other compute nodes, and wherein messages may be passed to the compute node using a point-to-point torus configuration.