METHOD TO EMBED PROTOCOL FOR SYSTEM MANAGEMENT BUS IMPLEMENTATION

• US 20080059682A1
• Filed: 08/31/2006
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Villarosa, Louis F., Cooley, Stephen, Kimmery, Clifford E.
• Application Number:
  US11/469,207
• Publication Number:
  US 20080059682A1
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method including embedding a component address having a length of up to seven bits in a System Management Bus Block Write and completing a system transaction with the System Management Bus Block Write and a second data packet so that data is sent between the control processor and the peripheral component having the component address.

Claims

1. A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method comprising:

embedding a component address having a length of up to seven bits in a System Management Bus Block Write; and

completing a system transaction with the System Management Bus Block Write and a second data packet, wherein data is sent between the control processor and the peripheral component having the component address.

2. The method of claim 1, wherein embedding a component address comprises:

embedding an address of an internal location of the peripheral component in address offset fields of the System Management Bus Block Write.

3. The method of claim 1, wherein the System Management Bus Block Write is a first System Management Bus Block Write, wherein the second data packet is a second System Management Bus Block Write, the method further comprising:

embedding a data word payload having a length of up to thirty-two bytes in the second System Management Bus Block Write, wherein the data word payload in the second System Management Bus Block Write is written to the peripheral component.

4. The method of claim 3, wherein embedding a data word comprises:

embedding the data word payload in data byte fields of the second System Management Bus Block Write.

5. The method of claim 3, further comprising:

decoding address offset bytes in address offset fields to determine at least one internal location of the addressed peripheral component; and

writing the data word payload to the internal location of the addressed peripheral component.

6. The method of claim 5, further comprising:

checking the protocol by comparing data in a block length field of the first System Management Bus Block Write with data in a byte count field of the second System Management Bus Block Write.

7. The method of claim 3, further comprising:

decoding a byte count field in the second System Management Bus Block Write to determine multiple word accesses.

8. The method of claim 1, wherein the second data packet is a System Management Bus Block Read, the method further comprising:

embedding an address of the peripheral component in a slave address field preceding a command code field and in a slave address field following the command code field of the System Management Bus Block Read; and

embedding a data word payload having a length of up to thirty-two bytes, wherein the data word payload is sent from the peripheral component in the System Management Bus Block Read responsive to the second address in the System Management Bus Block Read.

9. The method of claim 8, wherein embedding a data word comprises:

embedding the data word payload in data byte fields of the System Management Bus Block Read.

10. The method of claim 8, further comprising:

decoding bytes in the address offset fields to determine at least one internal location of the addressed peripheral component; and

sending the data word from the internal location of the addressed peripheral component.

11. The method of claim 8, further comprising:

checking the protocol by comparing data in a block length field of the System Management Bus Block Write with data in a byte count field of the System Management Bus Block Read.

12. The method of claim 8, further comprising:

decoding a byte count field in the System Management Bus Block Read to determine multiple word accesses.

13. A method of reading data from a peripheral component and writing data to a peripheral component, the method comprising:

transferring an address to a peripheral component in a system write command in data packets structured as a first SMBus Block Write;

transferring data to the peripheral component in the system write command in data packets structured as a second SMBus Block Write;

transferring an address to a peripheral component in a system read command in data packets structured as a SMBus Block Write;

transferring data from the peripheral component in the system read command in data packets structured as a SMBus Block Read; and

transferring address information and a number of data bytes accessed in a previous transaction of the peripheral component in data packets structured as a SMBus Block Read.

14. The method of claim 13, further comprising:

receiving the data packet at a peripheral component addressed by a first portion of an address block;

decoding a second portion of the address block in the data packet at the peripheral component; and

confirming the data packet is addressed to the peripheral component.

15. The method of claim 14, further comprising:

decoding address offset bytes to determine at least one internal location of the peripheral component being accessed by the data packet.

16. The method of claim 13, wherein transferring address information and a number of data bytes accessed in a previous transaction of the peripheral component in data packets structured as a SMBus Block Read comprises transferring an interrogation data packet, the method further comprising:

embedding an address of an internal location of the peripheral component used in the last transaction, the address of the internal location embedded in at least one address offset field of the SMBus Block Read; and

embedding the number of data bytes used by the peripheral component in the last transaction in the block length field of the SMBus Block Read.

17. A computer-readable medium having computer-executable instructions for performing a method comprising:

embedding an address of an internal location of a peripheral component in address offset fields having a length of up to seven bits in a System Management Bus Block Write; and

completing a system transaction with the System Management Bus Block Write and a second data packet wherein data is sent between a control processor and the peripheral component in to complete a system transaction.

18. The medium of claim 17, wherein the System Management Bus Block Write is a first System Management Bus Block Write and the second data packet is a second System Management Bus Block Write, wherein the method performed by the medium having computer-executable instructions further comprises:

embedding the data word payload in a range of four data byte fields to thirty-two data byte fields in the second System Management Bus Block Write, the data word payload having a length of up to thirty-two bytes, wherein the data word payload is written to the peripheral component.

19. The medium of claim 18, wherein the method performed by the medium having computer-executable instructions further comprises:

checking the protocol by comparing data in a block length field of the first System Management Bus Block Write with data in a byte count field of the second System Management Bus Block Write.

20. The medium of claim 17, wherein the second data packet is a System Management Bus Block Read, wherein the method performed by the medium having computer-executable instructions further comprises:

embedding an address of the peripheral component in a slave address field preceding a command code field and in a slave address field following the command code field of the System Management Bus Block Read; and

embedding the data word payload in a range of four data byte fields to thirty-two data byte fields in the System Management Bus Block Read, the data word payload having a length of up to thirty-two bytes, wherein the data word payload is sent from the peripheral component responsive to the second address in the System Management Bus Block Read.