Systems and methods for masking latency of memory reorganization work in a compressed memory system

• US 20080059728A1
• Filed: 09/06/2006
• Published: 03/06/2008
• Est. Priority Date: 09/06/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Daly, David Michael, Lastras-Montano, Luis Alfonso, Trombley, Michael Raymond, Franaszek, Peter Anthony, Ignatowski, Michael
• Granted Patent: US 8,122,216 B2
• Time in Patent Office: Days
• US Class Current: 711/158
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Claims

1. A computer system, comprising:

a main memory comprising first and second memory regions having different access characteristics;

a memory controller to manage the main memory and to allow access to stored data items in the main memory, wherein the memory controller implements a memory reorganization process comprising an execution flow of process steps for accessing a data item that is stored in one of the first or second memory region, and storing the accessed data item in the other one of the first or second memory region; and

a local buffer memory operated under control of the memory controller to temporarily buffer data items to be written to the main memory and data items read from the main memory during the memory reorganization process,

wherein the memory controller temporarily suspends the execution flow of the memory reorganization process between process steps, if necessary, according to a priority schedule, and utilizes the local buffer memory to temporarily store data that is to be processed when the memory reorganization process is resumed.

2. The computer system of claim 1, wherein at least one of the first and second memory regions stores compressed data items.

3. The computer system of claim 1, wherein at least one of the first and second memory regions store uncompressed data items.

4. The computer system of claim 1, wherein at least one of the first and second memory regions stores encrypted data.

5. The computer system of claim 1, wherein the local buffer memory stores information other than memory data items.

6. The computer system of claim 1, wherein the local buffer memory temporarily stores a memory address associated with a memory data item.

7. The computer system of claim 1, wherein the local buffer memory temporarily stores an execution state of a memory reorganization process.

8. The computer system of claim 1, wherein the memory controller controls an execution flow of the process steps associated with a pending memory reorganization process according to a priority schedule that can give higher priority to memory access operations that are initiated during execution of the pending memory reorganization process.

9. The computer system of claim 1, wherein in response to a memory access request, the memory controller directly accesses the first memory region, speculatively, to determine if a requested data item is stored in at a mapped address location (MAL) in the first memory region, and wherein the memory controller will locate and read the requested data item stored in the second memory region to serve said memory access request if said requested data item is not stored at the MAL in the first memory region and then generate a request to continue the memory reorganization process.

10. The computer system of claim 9, wherein the first memory region stores uncompressed data items and the second memory region stores compressed data items.

11. The computer system of claim 10, wherein the memory reorganization process includes a first sequence of process steps including:

a first process step of continuing reading and decompressing a remaining portion of a compressed data block A associated with the requested data item and buffering a decompressed data block A;

a second process step of updating metadata associated with the compressed data block A; and

a third process step of freeing memory in the second memory region, which was used for storing the compressed data block A.

12. The computer system of claim 11, wherein the memory reorganization process includes a second sequence of process steps including:

a first process step of reading an uncompressed data block B stored at the MAL in the first memory region associated with the requested data item whose speculative access resulted in miss;

a second process step of writing the buffered decompressed data block A to the MAL in the memory location from which the uncompressed data block B was read; and

freeing the buffer memory that was used for storing the decompressed data block A.

13. The computer system of claim 12, wherein the first and second sequence of process steps can operate in parallel, and wherein commencement of the second process step of the second sequence is delayed until completion of the first process step of the first sequence of process steps.

14. The computer system of claim 12, wherein the memory reorganization process includes a third sequence of process steps including:

a first process step of compressing the uncompressed data block B;

a second process step of reading metadata associated with the compressed data block B;

a third process step of selecting memory locations in the second memory region for storing the compressed data block B;

a fourth process step of storing the compressed data block B in the second memory region in the selected memory locations;

a fifth process step of updating the metadata associated with the compressed data block B; and

a sixth process step of freeing the buffer memory that was used for storing the compressed data block B.

15. The computer system of claim 14, wherein the fourth and fifth process steps of the third sequence can be executed in parallel, and wherein execution of the fourth and fifth process steps are delayed pending completion of the third process step of the third sequence

16. The computer system of claim 14, wherein execution of the third process step of the third sequence is delayed pending completion of the first and second process steps of the third sequence.

17. A compressed memory system, comprising:

a processor,

a first cache associated with the processor,

a memory controller associated with the cache,

a plurality of block buffers associated with the memory controller; and

a storage unit associated with the memory controller, the storage unit comprising an uncompressed memory portion for storing uncompressed data and a compressed memory portion for storing compressed data;

wherein each of the plurality of block buffers can store compressed data read from the compressed memory portion, or store uncompressed data read from the uncompressed memory portion;

wherein the memory controller can decompress the compressed data in the each of the plurality of block buffers to generate decompressed data, and write buffered decompressed data to the uncompressed memory portion;

wherein the memory controller can compress uncompressed data to generate buffered compressed data and write the buffered compressed data to the compressed memory portion.

18. The compressed memory system of claim 17, wherein the storage unit is part of a main memory associated with the memory controller.

19. The compressed memory system of claim 17, wherein the storage unit is part of a second cache that is higher-level than the first cache.

20. The compressed memory system of claim 17, wherein the compressed memory portion also stores uncompressed data.

21. The compressed memory system of claim 20, wherein the uncompressed data comprises data that is unable to be compressed.

22. The compressed memory system of claim 21, wherein each of the plurality of block buffers can store the uncompressed data from the compressed memory portion.

23. The compressed memory system of claim 17, wherein each of the plurality of block buffers can store the result of decompressing compressed data from the compressed memory portion, or store the result of compressing uncompressed data from the uncompressed memory portion.

24. A method of storing and retrieving compressed data in a compressed memory system, the compressed memory system comprising a processor, a cache associated with the processor, a memory controller associated with the cache, a storage unit associated with the memory controller, and a plurality of block buffers associated with the memory controller, the storage unit comprising an uncompressed memory portion and a compressed memory portion, the method comprising the steps of:

reading a first compression translation table (CTT) entry for a block of compressed data;

reading the block of compressed data from the compressed memory portion of the storage unit based on the first CTT entry;

storing the read block of compressed data in a first of the plurality of block buffers;

decompressing the stored block of compressed data;

writing the decompressed block of compressed data to the uncompressed memory portion of the storage unit;

reading a second CTT entry for a block of uncompressed data;

reading the block of uncompressed data from the uncompressed memory portion of the storage unit based on the second CTT entry;

storing the read block of uncompressed data in a second of the plurality of block buffers;

compressing the stored block uncompressed data; and

writing the compressed block of uncompressed data to the compressed memory portion of the storage unit.

25. A method of storing and retrieving compressed data in a compressed memory system, the compressed memory system comprising a processor, a cache associated with the processor, a memory controller associated with the cache, a storage unit associated with the memory controller, and a plurality of block buffers associated with the memory controller, the storage unit comprising an uncompressed memory portion and a compressed memory portion, the method comprising the steps of:

reading a first compression translation table (CTT) entry for a block of compressed data;

reading the block of compressed data from the compressed memory portion of the storage unit based on the first CTT entry;

decompressing the read block of compressed data;

storing the decompressed block of compressed data in a first of the plurality of block buffers;

writing the decompressed block of compressed data from the first of the plurality of block buffers to the uncompressed memory portion of the storage unit;

reading a second CTT entry for a block of uncompressed data;

reading the block of uncompressed data from the uncompressed memory portion of the storage unit based on the second CTT entry;

compressing the read block uncompressed data;

storing the compressed block of uncompressed data in a second of the plurality of block buffers; and

writing the compressed block of uncompressed data from the second of the plurality of block buffers to the compressed memory portion of the storage unit.