Method and Apparatus for Performing Improved Group Floating-Point Operations
First Claim
1. A processor comprising:
- a virtual memory addressing unit;
a data path;
a register file comprising a plurality of registers coupled to the data path;
an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path.
0 Assignments
0 Petitions
Accused Products
Abstract
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
-
Citations
54 Claims
-
1. A processor comprising:
- a virtual memory addressing unit;
a data path;
a register file comprising a plurality of registers coupled to the data path;
an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
- a virtual memory addressing unit;
-
39. A programmable processor capable of operation independent of another host processor, the programmable processor comprising:
- a virtual memory addressing unit;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file comprising a plurality of registers coupled to the data path;
a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer and group floating-point operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
- a virtual memory addressing unit;
-
50. A programmable processor capable of operation independent of another host processor, the programmable processor comprising:
- a virtual memory addressing unit;
a data path;
an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file comprising a plurality of registers coupled to the data path, the plurality of registers configurable to receive and store catenated data from the data path and communicate the catenated data to the data path, wherein the elemental width of the catenated data may be anyone of the following types;
8-bit, 16-bit, 32-bit and 64-bit integer type and 32-bit floating-point type;
a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer, group floating-point and group data handling operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on in parallel to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision. - View Dependent Claims (51, 52, 53, 54)
- a virtual memory addressing unit;
Specification