SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR HIGH SPEED DATA TRANSFER USING A PLURALITY OF EXTERNAL CLOCK SIGNALS

• US 20080059830A1
• Filed: 09/05/2006
• Published: 03/06/2008
• Est. Priority Date: 09/05/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E.
• Granted Patent: US 8,098,784 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Methods, systems and computer program products for high speed data transfer. Methods include receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a first frequency, a first edge and a second edge. A clock period of each external clock signal is the amount of time between any two successive first edges. Data is received on one or more signal links at a second frequency that is faster than the first frequency. The data includes a first data pulse and a second data pulse. The data is captured at the second frequency in response to the first edges and not the second edges of the external clock signals. The first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal.

Claims

1. A method for capturing data, the method comprising:

receiving a plurality of external clock signals including a first external clock signal and a second external clock signal, each external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of each external clock signal is the amount of time between any two successive first edges;

receiving data on one or more signal links at a second frequency that is faster than the first frequency, the data including a first data pulse and a second data pulse; and

capturing the data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal.

2. The method of claim 1 further comprising transmitting a plurality of data pulses on one or more second signal links, wherein the data is transmitted at a frequency faster than the first frequency.

3. The method of claim 2 wherein the second signal links are the signal links.

4. The method of claim 1 wherein the second frequency is equal to the number of external clock signals multiplied by the first frequency.

5. The method of claim 1 wherein the one or more signal links consist of one signal link.

6. The method of claim 1 wherein the one or more signal links include two or more signal links.

7. The method of claim 1 wherein each of the external clock signals consist of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

8. The method of claim 1 further comprising transforming the external clock signals into one or more internal clock signals and capturing the data in response to the internal clock signals, the internal clock signals at a higher frequency than the first frequency.

9. The method of claim 8 wherein the transforming includes applying a clock pulse shaper to the external clock signals.

10. The method of claim 1 wherein the receiving a plurality of external clock signals, the receiving data and the capturing data are performed at a memory device.

11. A system for capturing data, the system comprising:

a plurality of external clock ports for receiving external clock signals including a first external clock signal and a second external clock signal, each external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of each external clock signal is the amount of time between any two successive first edges;

one or more signal link ports for receiving data at a second frequency faster than the first frequency, the data including a first data pulse and a second data pulse; and

logic in communication with the plurality of external clock ports and the one or more signal link ports for facilitating;

capturing the data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal.

12. The system of claim 11 wherein the plurality of external clock ports, the one or more signal link ports and the logic are located on a memory device.

13. The system of claim 11 wherein the plurality of external clock ports, the one or more signal link ports and the logic are located on a buffer device.

14. The system of claim 11 wherein the plurality of external clock ports, the one or more signal link ports and the logic are located on a memory controller.

15. The system of claim 11 wherein the second frequency is equal to the number of external clock signals times the first frequency.

16. The system of claim 11 wherein the one or more signal links consist of one signal link.

17. The system of claim 11 wherein the one or more signal links include two or more signal links.

18. The system of claim 11 wherein each of the external clock signals consist of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

19. The system of claim 11 wherein the logic further facilitates transforming the external clock signals into one or more internal clock signals and capturing the data in response to the internal clock signals, the internal clock signals at a higher frequency than the first frequency.

20. The system of claim 19 wherein the transforming includes applying a clock pulse shaper to the external clock signals.

21. A service for deploying technology for high speed data transfer, the service comprising:

creating information for any one of making, using or selling technology for high speed data transfer, the technology including;

a plurality of external clock ports for receiving external clock signals including a first external clock signal and a second external clock signal, each external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of each external clock signal is the amount of time between any two successive first edges;

one or more signal link ports for receiving data at a second frequency faster than the first frequency, the data including a first data pulse and a second data pulse; and

logic in communication with the plurality of external clock ports and the one or more signal link ports for facilitating;

capturing the data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal; and

deploying said created information to one or more customers via a distribution process.

22. The service of claim 21, wherein the information comprises any one of circuit comprising the external clock ports, the signal link ports and the logic, a design of the circuit, electrical characteristics of the circuit, or a design rule associated with the circuit, wherein the information is distributed in a tangible form consisting of any one of an ASIC chip die, a hard copy document, a soft copy electronic document, an electronic transmission or via portable media, the portable media comprising any one of a CD, a DVD, a magnetic tape, a magnetic disk, or a FLASH memory.

23. A buffer device in a memory system, the buffer device comprising:

a plurality of external clock ports for receiving external clock signals including a first external clock signal and a second external clock signal, each external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of each external clock signal is the amount of time between any two successive first edges;

one or more signal link ports for receiving data at a second frequency faster than the first frequency, the data including a first data pulse and a second data pulse; and

logic in communication with the plurality of external clock ports and the one or more signal link ports for facilitating;

capturing the data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal.

24. The buffer device of claim 23 wherein the buffer device is in communication with a memory controller via a memory bus and the parallel data is received from the memory controller via the memory bus.

25. The buffer device of claim 23 wherein the buffer device is in communication with a memory device via a memory device interface

26. A computer program product for capturing data, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving a plurality of external clock signals including a first external clock signal and a second external clock signal, each external clock signal having a first frequency, a first edge and a second edge, wherein a clock period of each external clock signal is the amount of time between any two successive first edges;

receiving data on one or more signal links at a second frequency that is faster than the first frequency, the data including a first data pulse and a second data pulse; and

capturing the data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data pulse is captured based on the first edge of the first external clock signal and the second data pulse is captured based on the first edge of the second external clock signal.

27. The computer program product of claim 26 wherein the method further comprises transmitting a plurality of data pulses on one or more second signal links, wherein the data is transmitted at a frequency faster than the first frequency.

28. The computer program product of claim 27 wherein the second signal links are the signal links.

29. The computer program product of claim 26 wherein the second frequency is equal to the number of external clock signals multiplied by the first frequency.

30. The computer program product of claim 26 wherein the one or more signal links consist of one signal link.

31. The computer program product of claim 26 wherein the one or more signal links include two or more signal links.

32. The computer program product of claim 26 wherein each of the external clock signals consist of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

33. The computer program product of claim 26 wherein the method further comprises transforming the external clock signals into one or more internal clock signals and capturing the data in response to the internal clock signals, the internal clock signals at a higher frequency than the first frequency.

34. The computer program product of claim 33 wherein the transforming includes applying a clock pulse shaper to the external clock signals.

35. The computer program product of claim 26 wherein the receiving a plurality of external clock signals, the receiving data and the capturing data are performed at a memory device.