Semiconductor Device with Heterojunctions and an Inter-Finger Structure

• US 20080061293A1
• Filed: 01/18/2006
• Published: 03/13/2008
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Energies Alternatives Commissariat A L'Energie Atomique et AUX
• Inventors: Ribeyron, Pierre, Jaussaud, Claude
• Granted Patent: US 7,935,966 B2
• Time in Patent Office: Days
• US Class Current: 257/53
• CPC Class Codes: H01L 31/022433 Particular geometry of the grid contacts
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/0288 characterised by the doping material
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/0745 comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
• CPC Class Codes: H01L 31/0747 comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
• CPC Class Codes: H01L 31/202 including only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device including, on at least one surface of a crystalline semiconductor substrate, at least one first amorphous semiconductor region doped with a first type of conductivity. The semiconductor substrate includes, on the same at least one surface, at least one second amorphous semiconductor region doped with a second type of conductivity, opposite the first type of conductivity. The first amorphous semiconductor region, insulated for the second amorphous semiconductor region by at least ore dielectric region in the contact with the semiconductor substrate, and the second amorphous semiconductor region form an interdigitated structure.

Claims

1-38. -38. (canceled)

39. A semiconductor device comprising, on at least one surface of a crystalline semiconductor substrate:

at least one first amorphous semiconductor region doped with a first type of conductivity, which semiconductor substrate comprises, on the same at least one surface, at least one second amorphous semiconductor region doped with a second type of conductivity, opposite the first type of conductivity,

wherein the first amorphous semiconductor region, insulated from the second amorphous semiconductor region by at least one dielectric region in contact with the semiconductor substrate also ensuring passivation of the surface of the substrate, and the second amorphous semiconductor region form an interdigitated structure.

40. A semiconductor device according to claim 39, the dielectric region being made of silicon oxide, silicon nitride, or amorphous crystalline silicon.

41. A semiconductor device according to claim 39, further comprising at least one first metallization area in contact with the first amorphous semiconductor region, and at least one second metallization area in contact with the second amorphous semiconductor region.

42. A semiconductor device according to claim 41, further comprising at least one first conductive thermal oxide area located between the first metallization area and the first amorphous semiconductor region, and at least one second conductive thermal oxide area located between the second metallization area and the second amorphous semiconductor region.

43. A semiconductor device according to claim 42, the conductive thermal oxide areas being made of indium and tin oxide or zinc oxide.

44. A semiconductor device according to claim 41, the metallization areas being based on a noble metal, based on silver, or based on aluminium.

45. A semiconductor device according to claim 39, the semiconductor substrate further comprising, on another surface, opposite the surface having the interdigitated structure, a surface passivation layer coated with an antireflective layer.

46. A semiconductor device according to claim 45, the surface passivation layer being made of an intrinsic amorphous semiconductor with the first type of conductivity or the second type of conductivity.

47. A semiconductor device according to claim 46, the surface passivation layer being made of silicon.

48. A semiconductor device according to claim 45, the antireflective layer being made of silicon nitride.

49. A semiconductor device according to claim 39, the first amorphous semiconductor region and/or the second amorphous semiconductor region being doped gradually.

50. A semiconductor device according to claim 39, the semiconductor substrate being made of monocrystalline silicon or polycrystalline silicon.

51. A semiconductor device according to claim 39, the amorphous semiconductor regions being made of silicon.

52. A semiconductor device according to claim 39, the semiconductor substrate being of a certain type of conductivity.

53. A semiconductor device according to claim 39, the semiconductor substrate being a thin-layer substrate.

54. A semiconductor device according to claim 39, further comprising intrinsic semiconductor regions placed between the amorphous semiconductor regions and the substrate.

55. A semiconductor device according to claim 39, the semiconductor device being a solar cell.

56. A module of solar cells, comprising a plurality of solar cells according to claim 55, connected in series and/or in parallel.

57. A method for producing a semiconductor device, comprising:

a) producing a first insulating layer on a surface of a semiconductor substrate;

b) etching, in the first insulating layer, at least one first window exposing a portion of the semiconductor substrate;

c) depositing a first amorphous semiconductor layer doped with a first type of conductivity on the first insulating layer and in the first window;

d) etching, in the first amorphous semiconductor layer and the first insulating layer, at least one second window, offset from the first window, exposing a portion of the semiconductor substrate;

e) producing a second insulating layer in the second window and on the first amorphous semiconductor layer;

f) etching at least one first opening in the second insulating layer, at a level of the second window, exposing a portion of the semiconductor substrate; and

g) depositing a second amorphous semiconductor or layer doped with a second type of conductivity opposite the first type of conductivity in the first opening, and on the second insulating layer;

wherein the first amorphous semiconductor layer and the second amorphous semiconductor layer form an interdigitated structure having a contour defined by the etching of the first window and the first opening.

58. A method according to claim 57, further comprising, between b) and c), depositing at least one first intrinsic semiconductor region at least in the first window and/or, between f) and g), depositing at least one second intrinsic semiconductor region at least in the first opening.

59. A method according to claim 57, further comprising, between c) and d), or between d) and e), depositing at least one first metallization area on the first amorphous semiconductor layer.

60. A method according to claim 57, further comprising, between c) and d), or between d) and e), depositing at least one first conductive thermal oxide area on the first amorphous semiconductor layer, and then depositing at least one first metallization area on the first conductive thermal oxide area.

61. A method according to claim 59, the first metallization area being centered above the first window.

62. A method according to claim 59, a size of the first metallization area being smaller than that of the first window.

63. A method according to claim 59, further comprising, after g), etching at least one second opening in the second amorphous semiconductor layer and in the second insulating layer, above the first metallization area, of which a size is smaller than or equal to that of the first metallization area, exposing at least a portion of the first metallization area.

64. A method according to claim 59, further comprising, after g), depositing at least one second metallization area on the second amorphous semiconductor layer, at a level of the second window, on at least the first opening.

65. A method according to claim 59, further comprising, after g), depositing at least one second conductive thermal oxide area on the second amorphous semiconductor layer, at a level of the second window, on at least the first opening, and then depositing at least one second metallization area on the second conductive thermal oxide area.

66. A method according to claim 57, the first opening being smaller than the second window.

72. A method according to claim 57, further comprising:

depositing the semiconductor substrate of a surface passivation layer onto another surface, opposite to the surface of the semi-conductor substrate having the interdigitated structure; and

depositing an antireflective layer on the surface passivation layer.

73. A method according to claim 72, the depositing the surface passivation layer and the antireflective layer being performed before a).

74. A method according to claim 57, at least one etching operation being performed by laser or by serigraphy with etching pastes.

75. A method according to claim 57, at least one etching operation being a selective etching operation making it possible to etch the amorphous semiconductor and not the metal.

76. A method according to claim 57, the semiconductor substrate being first chemically cleaned by a conventional RCA cleaning and a hydrofluoric acid cleaning before a).

67. A method for producing a semiconductor device, comprising:

a) depositing at least one first amorphous semiconductor layer doped with a first type of conductivity on a surface of a semiconductor substrate;

b) depositing at least one first metallization area on at least the first amorphous semiconductor layer;

c) removing areas of the first amorphous semiconductor layer not covered by the first metallization area;

d) depositing at least one second amorphous semiconductor layer doped with a second type of conductivity opposite the first type of conductivity on at least the surface of the substrate;

e) depositing at least one second metallization area on at least the second amorphous semiconductor layer;

f) removing areas of the second amorphous semiconductor layer not covered by the second metallization area; and

g) depositing a dielectric insulating layer on at least one surface of the substrate, also ensuring passivation of the surface of the substrate;

wherein the first amorphous semiconductor layer and the second amorphous semiconductor layer form an interdigitated structure.

68. A method according to claim 67, further comprising, after g), depositing the insulating layer, producing openings in the insulating layer at a level of the metallization areas.

69. A method according to claim 67, further comprising, before a), depositing at least one intrinsic semiconductor layer on the surface of the substrate, the first amorphous semiconductor layer being then deposited on the intrinsic semiconductor layer, and c) also including removal of areas of the intrinsic semiconductor layer not covered by the first metallization area.

70. A method according to claim 69, further comprising, between c) and d), depositing at least one second intrinsic semiconductor layer on at least the surface of the substrate, the second amorphous semiconductor layer being then deposited on the second intrinsic semiconductor layer, and f) also including removal of areas of the second intrinsic semiconductor layer not covered by the second metallization area.

71. A method according to claim 67, wherein in at least one of c) and/or f) the removing semiconductor areas is performed by etching.