Transistor, Memory Cell Array and Method of Manufacturing a Transistor

• US 20080061320A1
• Filed: 09/07/2007
• Published: 03/13/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: von Kluge, Johannes, Tegen, Stefan
• Granted Patent: US 7,763,514 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.

Claims

1. An integrated circuit including a transistor, the transistor comprising:

first and second source/drain regions formed in a semiconductor substrate and extending to a first depth with respect to a top surface of the substrate;

a channel region connecting the first and second source/drain regions; and

a gate electrode disposed in a gate groove defined in the top surface of the substrate between the first and second source/drain regions;

wherein a top surface of the gate electrode is disposed between the top surface of the substrate and the first depth.

2. The integrated circuit of claim 1, wherein:

the channel region comprises a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and

the gate electrode surrounds the ridge at the top side and the two lateral sides.

3. The integrated circuit of claim 1, further comprising:

a spacer comprising a dielectric material, the spacer being disposed adjacent a sidewall of the gate groove and located between the gate electrode and the semiconductor substrate, wherein a bottom side of the spacer is disposed at a depth no greater than the first depth.

4. The integrated circuit of claim 1, further comprising:

two spacer structures comprising a dielectric material and disposed on opposing sidewalls of the gate groove, wherein a bottom edge of the spacer structures is disposed at a lesser distance from the top surface of the substrate than a bottom of the gate groove;

wherein the distance between inner edges of the spacer structures corresponds to a width of a portion of the gate groove disposed below the bottom edge of the spacer structures and along a first direction, the first direction being defined by a line extending between the first and second source/drain regions.

5. The integrated circuit of claim 4, wherein the spacer structures are oxide spacers.

6. The integrated circuit of claim 5, wherein the spacer structures are thermally grown silicon dioxide spacers.

7. The integrated circuit of claim 1, further comprising:

at least one vacuum spacer disposed adjacent one of the sidewalls of the gate groove and located between the gate electrode and the semiconductor substrate, wherein a bottom side of the vacuum spacer is disposed at a depth no greater than the first depth.

8. The integrated circuit of claim 1, wherein the gate electrode encloses a portion of the channel region on three sides.

9. An integrated circuit including a memory cell array comprising:

a plurality of bitlines running along a first direction;

a plurality of memory cells, each of the memory cells comprising a storage element and an access transistor configured to electrically couple the storage element to one of the bit lines, wherein the access transistors are formed in a semiconductor substrate and comprise doped portions arranged adjacent a top surface of the semiconductor substrate and extending to a first depth; and

a plurality of word lines configured to address the access transistors and running along a second direction intersecting the first direction, wherein a top surface of each of the word lines is disposed at a depth between the top surface of the substrate and the first depth.

10. The integrated circuit of claim 9, wherein a plurality of isolation trenches is formed in the semiconductor substrate to define active areas between the isolation trenches, wherein the isolation trenches are configured to insulate adjacent active areas from each other, and the access transistors are formed in the active areas.

11. The integrated circuit of claim 9, wherein the storage elements comprise storage capacitors formed in the semiconductor substrate.

12. The integrated circuit of claim 9, wherein the storage elements comprise storage capacitors formed above the semiconductor substrate.

13. The integrated circuit of claim 9, wherein:

the doped portions of each of the access transistors comprise a first source/drain region and a second source/drain region;

a channel is formed between the first and second source/drain regions of each access transistor; and

each of the access transistors further comprises a gate electrode configured to control an electrical current flowing in the channel, wherein the gate electrode forms part of a corresponding word line.

14. The integrated circuit of claim 13, wherein each gate electrode is disposed in a gate groove extending in the top surface of the substrate between the first and second source/drain regions of each access transistor.

15. An integrated circuit comprising a transistor that is formed in a semiconductor substrate including a top surface, the transistor comprising:

a first source/drain region and a second source/drain region;

a channel region connecting the first and second source/drain regions; and

a gate electrode disposed in a gate groove defined in the top surface of the semiconductor substrate, wherein a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate; and

two spacer structures disposed on opposing sidewalls of the gate groove, wherein a bottom edge of the spacer structures is disposed above a bottom of the gate groove, and wherein a distance between inner edges of the spacer structures corresponds to a width of a portion of the gate groove below the bottom side of the spacer structures along a first direction defined by a line extending between the first and second source/drain regions.

16. The integrated circuit of claim 15, wherein an insulating material is disposed between the top surface of the gate electrode and the top surface of the semiconductor substrate.

17. The integrated circuit of claim 15, wherein the spacer structures are oxide spacers.

18. The integrated circuit of claim 15, wherein the spacer structures are thermally grown silicon dioxide spacers.

19. A method of fabricating an integrated circuit including a transistor, the method comprising:

forming a gate groove extending in a surface of a semiconductor substrate;

forming a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the first and second source/drain regions are adjacent the substrate surface and extend to a first depth as measured from the substrate surface;

forming a spacer on a sidewall of the gate groove, wherein the spacer extends from the substrate surface to a depth which is less than the first depth; and

forming a gate electrode in the gate groove, wherein a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate at a second depth which is less than the first depth, the second depth being measured from the substrate surface, wherein an upper groove portion is defined above the gate electrode.

20. The method of claim 19, further comprising:

filling the upper groove portion with an insulating material.

21. The method of claim 20, wherein the spacer is removed subsequent to providing the gate electrode and prior to filling the upper groove portion with an insulating material.

22. The method of claim 21, wherein filling the upper groove portion with an insulating material comprises non-conformally depositing the insulating material.

23. The method of claim 19, wherein:

forming a gate groove comprises etching a first groove in the substrate surface and vertically extending the first groove; and

the spacer is formed subsequent to etching the first groove and prior to vertically extending the first groove.

24. The method of claim 19, wherein forming a gate groove comprises etching a first groove in the substrate surface, and vertically extending the first groove by anisotropic etching of the semiconductor substrate.

25. A method of forming an integrated circuit including a transistor, the method comprising:

forming a first groove in a semiconductor substrate;

forming a spacer structure extending along a vertical sidewall of the first gate groove;

vertically extending the first groove to form a second groove, the first groove and the second groove forming a gate groove, wherein the spacer structure is effective as an etch mask; and

forming a gate electrode in the gate groove.

26. The method of claim 25, wherein two spacer structures are formed on opposing sidewalls of the first groove.

27. The method of claim 26, wherein a top surface of the gate electrode is formed between the substrate surface and a lower edge of the sidewall spacers.

28. The method of claim 26, further comprising:

removing the spacer structures after forming the gate electrode.

29. The method of claim 28, further comprising:

depositing an inconformal insulating layer to fill the gate groove at least partially above the top surface of the gate electrode.

30. The method of claim 26, wherein the spacer structures are formed by thermal oxidation of the semiconductor substrate.