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Transistor, Memory Cell Array and Method of Manufacturing a Transistor

  • US 20080061320A1
  • Filed: 09/07/2007
  • Published: 03/13/2008
  • Est. Priority Date: 09/08/2006
  • Status: Active Grant
First Claim
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1. An integrated circuit including a transistor, the transistor comprising:

  • first and second source/drain regions formed in a semiconductor substrate and extending to a first depth with respect to a top surface of the substrate;

    a channel region connecting the first and second source/drain regions; and

    a gate electrode disposed in a gate groove defined in the top surface of the substrate between the first and second source/drain regions;

    wherein a top surface of the gate electrode is disposed between the top surface of the substrate and the first depth.

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