Transistor, memory cell array and method of manufacturing a transistor

• US 20080061322A1
• Filed: 09/08/2006
• Published: 03/13/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: von Kluge, Johannes
• Granted Patent: US 7,612,406 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.

Claims

1. A transistor formed in a semiconductor substrate, the semiconductor substrate including a top surface, the transistor comprising:

a first source/drain region and a second source/drain region;

a channel connecting the first and second source/drain regions; and

a gate electrode to control an electrical current flowing in the channel, wherein the gate electrode is disposed in a gate groove, the gate groove being defined in the top surface of the semiconductor substrate;

wherein;

the first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate; and

a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.

2. The transistor of claim 1, wherein the channel comprises a fin-like portion including a ridge, the ridge comprises a top side and two lateral sides in a cross-section perpendicular to a first direction, the first direction is defined by a line extending between the first and second source/drain regions, and the gate electrode is at least partially surrounded by the channel at the top side and the two lateral sides.

3. The transistor of claim 1, further comprising a spacer comprising a dielectric material, wherein the spacer is disposed adjacent a sidewall of the gate groove and located between the gate electrode and the semiconductor substrate, and a bottom side of the spacer is disposed at a depth no greater than d1.

4. The transistor of claim 1, further comprising a vacuum spacer, wherein the spacer is disposed adjacent a sidewall of the gate groove and located between the gate electrode and the semiconductor substrate, and a bottom side of the vacuum spacer is disposed at a depth no greater than d1.

5. A memory cell array comprising:

a plurality of memory cells, each of the memory cells comprising a storage element and an access transistor;

a plurality of bit lines running along a first direction;

a plurality of word lines running along a second direction, wherein the second direction intersects the first direction; and

a semiconductor substrate including a top surface;

wherein the access transistors are formed in the semiconductor substrate, the access transistors electrically couple corresponding storage elements to corresponding bit lines, the access transistors are addressed by the word lines, the access transistors comprise doped portions that are arranged adjacent the substrate surface, the doped portions extend to a depth d1, a top surface of each of the word lines is disposed beneath the top surface of the semiconductor substrate, and the top surface of each of the word lines is disposed at a depth d2 which is less than the depth d1, the depths d1 and d2 being measured from the top surface of the substrate.

6. The memory cell array of claim 5, wherein a plurality of isolation trenches are formed in the semiconductor substrate to define active areas between the isolation trenches, wherein the isolation trenches are adapted to insulate adjacent active areas from each other, and the access transistors are formed in the active areas.

7. The memory cell array of claim 5, wherein the storage elements comprise storage capacitors formed in the semiconductor substrate.

8. The memory cell array of claim 5, wherein the storage elements comprise storage capacitors formed above the semiconductor substrate.

9. The memory cell array of claim 5, wherein the doped portions of each of the access transistors comprise first source/drain regions and second source/drain regions, a channel is formed between the first and second source/drain regions of each access transistor, and each of the access transistors further comprises a gate electrode to control an electrical current flowing in the channel, the gate electrode forming part of a corresponding word line.

10. The memory cell array of claim 9, wherein each gate electrode is disposed in a gate groove extending in the substrate surface between the first and the second source/drain region of each access transistor.

11. A transistor that is formed in a semiconductor substrate including a top surface, the transistor comprising:

a first source/drain region and a second source/drain region;

a channel connecting the first and second source/drain regions; and

a gate electrode to control an electrical current flowing in the channel, wherein the gate electrode is disposed in a gate groove, the gate groove is defined in the top surface of the semiconductor substrate, a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate, an upper groove portion is disposed above the top surface of the gate electrode and beneath the top surface of the semiconductor substrate, and the width of the upper groove portion is larger than the width of the gate electrode, the widths of the upper groove portion and the gate electrode being measured along a first direction that is defined by a line extending between the first and second source/drain regions.

12. The transistor of claim 11, wherein the upper groove portion is filled with an insulating material.

13. The transistor of claim 12, wherein the gate electrode comprises a gate-insulating layer and a gate conductive material, the gate-insulating layer being disposed between the gate conductive material and the semiconductor substrate.

14. A method of forming a transistor comprising:

providing a semiconductor substrate including a surface;

providing a gate groove extending in the substrate surface;

providing a first source/drain region and a second source/drain region, wherein the first and the second source/drain regions are adjacent the substrate surface and extend to a depth d1 as measured from the substrate surface;

providing a sacrificial spacer on a sidewall of the gate groove, wherein the sacrificial spacer extends from the substrate surface to a depth which is less than d1;

providing a gate electrode including a top surface that is disposed beneath the top surface of the semiconductor substrate at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface, wherein an upper groove portion is disposed above the gate electrode; and

filling the upper groove portion with an insulating material.

15. The method of claim 14, wherein filling the upper groove portion with an insulating material comprises non-conformally depositing the insulating material.

16. The method of claim 14, wherein providing a gate groove comprises etching a first groove in the substrate surface and vertically extending the first groove, and the sacrificial spacer is provided after etching the first groove and before vertically extending the first groove.

17. The method of claim 14, wherein providing a gate groove comprises etching a first groove in the substrate surface, and vertically extending the first groove by anisotropic etching of the substrate material.

18. The method of claim 14, wherein the sacrificial spacer is removed after providing the gate electrode and before filling the upper groove portion with an insulating material.

19. A transistor that is formed in a semiconductor substrate including a top surface, the transistor comprising:

a first doped region and a second doped region;

a channel connecting the first and second doped regions; and

means for controlling an electrical current flowing in the channel, wherein the means for controlling the electrical current is disposed in a groove, the groove being defined in the top surface of the semiconductor substrate;

wherein the first and second doped regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate, a top surface of the means for controlling the electrical current is disposed beneath the top surface of the semiconductor substrate, and the top surface of the means for controlling an electrical current is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.

20. The transistor of claim 19, further comprising means for shielding an electrical field of the means for controlling the electrical current from the first and second doped regions.

21. The transistor of claim 20, wherein a bottom side of the means for shielding the electrical field is disposed at a depth which is no greater than d1.