Examination apparatus for biological sample and chemical sample

• US 20080061323A1
• Filed: 10/29/2007
• Published: 03/13/2008
• Est. Priority Date: 01/21/2004
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Watanabe, Kazuki, Kamahori, Masao, Yazawa, Yoshiaki, Kunimoto, Yukinori
• Granted Patent: US 7,888,708 B2
• Time in Patent Office: Days
• US Class Current: 257/253
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10K 30/671 Organic radiation-sensitive molecular electronic devices

Abstract

A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a PMOS transistor is formed and a p type semiconductor layer on which an nMOS transistor is formed are isolated by a pn junction. Therefore, the p type semiconductor layer at the outermost portion (chip edge portion to be in contact with solution) is set to floating, and the maximum potential and the minimum potential of the chip are supplied to an n type semiconductor layer and a p type semiconductor layer inside the outermost portion, respectively. Also, the chip is covered with an ion impermeable insulating film for reducing the penetration of positive ions through the oxide layer.

Claims

1. An unpackaged semiconductor integrated circuit device formed to be used in a solution, and having an SOI substrate in which a support substrate, a buried insulating layer, and a semiconductor layer are stacked thereon in order, and an integrated circuit is formed on said semiconductor layer, comprising:

a guard ring layer which is formed with an n-type impurity diffusion layer in said semiconductor layer and which surrounds a formation area of said integrated circuit, said guard ring reaching said buried insulating layer; and

a floating layer which is formed with an p-type impurity diffusion layer in said semiconductor layer and which surrounds said guard ling layer, an inside surface of said floating layer being in contact with an outside surface of said guard ring layer, and said floating layer reaching an outer surface of said semiconductor layer,

wherein said guard ring is set to a maximum potential of said integrated circuit, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said outer surface of said semiconductor layer is exposed to said solution.

2. The unpackaged semiconductor integrated circuit device according to claim 1,

wherein said integrated circuit includes an ion sensitive field effect transistor and an ion sensitive film which is electrically connected to a gate of said ion sensitive field effect transistor, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said ion sensitive film is exposed to said solution instead of said outer surface of said semiconductor layer.

3. The unpackaged semiconductor integrated circuit device according to claim 1,

wherein said integrated circuit includes a first ion sensitive field effect transistor, a second ion sensitive field effect transistor, a first ion sensitive film electrically connected to a gate of said first ion sensitive field effect transistor, and a second ion sensitive film electrically connected to a gate of said second ion sensitive field effect transistor,

wherein, an ion selectivity of said first ion sensitive film is different from an ion selectivity of said second sensitive film, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said first and second ion sensitive films are exposed to said solution instead of said outer surface of said semiconductor layer.

4. The unpackaged semiconductor integrated circuit device according to claim 1,

wherein said integrated circuit includes an ion sensitive field effect transistor, a metal layer which is electrically connected to a gate of said ion sensitive field effect transistor and a probe DNA attached to said metal layer, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said metal layer and said probe DNA are exposed to said solution instead of said outer surface of said semiconductor layer.

5. An unpackaged semiconductor integrated circuit device formed to be used in a solution, and having an SOI substrate in which a support substrate, a buried insulating layer, and a semiconductor layer are stacked thereon in order, and an integrated circuit being formed on said semiconductor layer, comprising:

a guard ring layer which is formed with an p-type impurity diffusion layer in said semiconductor layer, and which surrounds a formation area of said integrated circuit, said guard ring reaching said buried insulating layer; and

a floating layer which is formed with an n-type impurity diffusion layer in said semiconductor layer, and which surrounds said guard ling layer, wherein an inside surface of said floating layer is in contact with an outside surface of said guard ring layer, said floating layer reaching an outer surface of said semiconductor layer,

wherein said guard ring is set to a minimum potential of said integrated circuit, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said outer surface of said semiconductor layer is exposed to said solution.

6. The unpackaged semiconductor integrated circuit device according to claim 5,

wherein said integrated circuit includes an ion sensitive field effect transistor and an ion sensitive film which is electrically connected to a gate of said ion sensitive field effect transistor, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said ion sensitive film is exposed to said solution instead of said outer surface of said semiconductor layer.

7. The unpackaged semiconductor integrated circuit device according to claim 5,

wherein said integrated circuit includes a first ion sensitive field effect transistor, a second ion sensitive field effect transistor, a first ion sensitive film electrically connected to a gate of said first ion sensitive field effect transistor, and a second ion sensitive film electrically connected to a gate of said second ion sensitive field effect transistor,

wherein, an ion selectivity of said first ion sensitive film is different from an ion selectivity of said second sensitive film, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said first and second ion sensitive films are exposed to said solution instead of said outer surface of said semiconductor layer.

8. The unpackaged semiconductor integrated circuit device according to claim 5,

wherein said integrated circuit includes an ion sensitive field effect transistor, a metal layer electrically connected to a gate of said ion sensitive field effect transistor and a probe DNA attached to said metal layer, and

wherein, when said unpackaged semiconductor integrated circuit device is used, said metal layer and said probe DNA are exposed to said solution instead of said outer surface of said semiconductor layer.