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Method of reducing memory cell size for non-volatile memory device

  • US 20080061358A1
  • Filed: 03/01/2007
  • Published: 03/13/2008
  • Est. Priority Date: 03/02/2006
  • Status: Abandoned Application
First Claim
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1. A non-volatile NAND Flash memory cell comprising:

  • a substrate having a first doped materials;

    a lightly second doped junction regions near the said substrate surface;

    a stacked oxide -nitride-oxide overlaying the second doped surface junction region of the memory cell;

    a control gate overlaying a stacked oxide -nitride-oxide of the memory cell; and

    a self aligned spacer in the side wall of a control gate over a stacked oxide-nitride-oxide on the substrate of the memory cell in order to isolate the adjacent control gates.

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