Method of reducing memory cell size for non-volatile memory device
First Claim
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1. A non-volatile NAND Flash memory cell comprising:
- a substrate having a first doped materials;
a lightly second doped junction regions near the said substrate surface;
a stacked oxide -nitride-oxide overlaying the second doped surface junction region of the memory cell;
a control gate overlaying a stacked oxide -nitride-oxide of the memory cell; and
a self aligned spacer in the side wall of a control gate over a stacked oxide-nitride-oxide on the substrate of the memory cell in order to isolate the adjacent control gates.
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Abstract
In accordance with the present invention, a new method, its structure and manufacturing method is proposed to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.
22 Citations
18 Claims
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1. A non-volatile NAND Flash memory cell comprising:
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a substrate having a first doped materials;
a lightly second doped junction regions near the said substrate surface;
a stacked oxide -nitride-oxide overlaying the second doped surface junction region of the memory cell;
a control gate overlaying a stacked oxide -nitride-oxide of the memory cell; and
a self aligned spacer in the side wall of a control gate over a stacked oxide-nitride-oxide on the substrate of the memory cell in order to isolate the adjacent control gates.
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2. The memory cell structure of claim 2 wherein said the first control gate and the self-aligned control gate is formed as polysilicon, or polycide or both combinations of polysilicon and polycide thereon.
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3. A string of non-volatile NAND Flash memory cells comprising:
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a substrate having a first doped materials;
forming highly second doped source and drain junction regions overlaying the first doped substrate;
forming a first dielectric material on the surface of said the substrate;
forming a selective gates between the second highly doped region on the surface of said the substrate;
forming a second lightly doped junction regions overlaying the said first doped substrate;
forming a control gate overlaying the stacked oxide -nitride-oxide on the substrate;
forming self aligned spacers in the side walls of a control gate on a stacked oxide-nitride-oxide on the substrate; and
forming a secondary dielectric materials between the select gate and the control gates of the memory cell. - View Dependent Claims (4, 5)
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6. A method making a series of NAND memory cells structure comprising:
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forming, through masking steps and ion implantation processes, a first n-well in a semiconductor substrate, forming a first p-well overlaying the first n-well, in a semiconductor substrate;
forming a non-volatile device region by removing either deposited material or materials or grown oxide layer down to surface of the substrate using a mask step;
forming a low doped surface junction for the said non-volatile device region by ion implantation;
forming a first spacer above the body region and adjacent said first polysilicon layer to isolate said memory region;
forming a stacked oxide-nitride-CVD on said the first control gate region;
forming a second polysilicon layer above said the stacked oxide-nitride oxide;
forming a first NAND control gate by etching above said the second polysilicon, and said the stacked oxide-nitride-oxide using mask step processes;
forming a second spacer above the first control gate region and adjacent said the first control gate on the stacked oxide-nitride-oxide;
forming a stacked oxide-nitride-oxide overlaying the entire said substrate;
forming a third polysilicon overlaying the stacked oxide-nitride-oxide overlaying the entire said substrate;
forming a second self-aligned NAND control gate by etch back process for the said entire bodies on the substrate. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A method making a string of NAND memory cells structure comprising:
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forming at least two isolation regions in a semiconductor substrate;
forming, through masking steps and ion implantation processes, a first n-well in a semiconductor substrate, forming a first p-well overlaying the first n-well, forming a second highly doped p-well near the first n-well and the first p-well, forming a second highly doped p-well near the first n-well and the first p-well, forming a second highly doped n-well, and forming a third highly doped n-well regions to define a body region;
forming a first oxide layer or a third oxide layer by using several masking steps above the body region;
forming a first polysilicon layer above said first oxide layer and above said third oxide layer;
forming a non-volatile device region by removing the first polysilicon, the first oxide and the third oxide layer on the substrate using a mask step;
forming a low doped surface junction for the said non-volatile device region by ion implantation;
forming a first spacer above the body region and adjacent said first polysilicon layer;
forming a stacked oxide-nitride-CVD on said the first control gate region;
forming a second polysilicon layer above said the stacked oxide-nitride oxide;
forming a first NAND control gate by etching above said the second polysilicon, and said the stacked oxide-nitride-oxide using mask step processes;
forming a second spacer above the first control gate region and adjacent said the first control gate on the stacked oxide-nitride-oxide;
forming a stacked oxide-nitride-oxide overlaying the entire said substrate;
forming a third polysilicon overlaying the stacked oxide-nitride-oxide overlaying the entire said substrate;
forming a second self-aligned NAND control gate by etch back process for the said entire bodies on the substrate;
forming transistor gates for the low voltages and high voltage over the said the first oxide and the third oxide. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification