Trench fet with self aligned source and contact

• US 20080061365A1
• Filed: 11/05/2007
• Published: 03/13/2008
• Est. Priority Date: 09/05/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thapar, Naresh, Amali, Adam
• Granted Patent: US 7,397,083 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Claims

1. A semiconductor device comprising:

a semiconductor body of a first conductivity which includes a channel region of a second conductivity and a major surface;

an active region formed in said semiconductor body, said active region including a plurality of spaced trenches extending through said channel region;

a gate structure disposed in each said trench, each gate structure including a gate oxide layer disposed at least on sidewalls of a trench and a gate electrode disposed adjacent said gate oxide layer;

conductive regions of said first conductivity formed in said channel region adjacent each said trench;

highly doped contact regions of said second conductivity formed in said channel region each being laterally confined between two opposing conductive regions;

a metallic contact in contact with said conductive regions and said highly doped contact regions; and

a termination structure, said termination structure including,

a termination trench having a slanted sidewall formed in said semiconductor body, and a grown field oxide layer formed in said termination trench below said major surface, a polysilicon field plate formed over said field oxide layer, and a low temperature oxide body over said polysilicon field plate, wherein said field oxide layer is thicker than said gate oxide layer, wherein said metallic contact extends over said low temperature oxide body, and wherein said semiconductor body of said first conductivity extends from said trench to the bottom of said termination trench.

2. A semiconductor device according to claim 1, wherein said trench includes an oxide mass formed at its bottom, said oxide mass being thicker than said gate oxide layer.

3. A semiconductor device according to claim 2, further comprising a semiconductor substrate of said first conductivity, said semiconductor body being formed over said semiconductor substrate, wherein said conductive regions are electrically connectable to said semiconductor substrate through invertible channels adjacent said trench.

4. A semiconductor device according to claim 3, wherein said conductive regions are source regions.

5. A semiconductor device according to claim 1, further comprising an oxide plug disposed over each gate electrode.