COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20080061366A1
• Filed: 09/11/2006
• Published: 03/13/2008
• Est. Priority Date: 09/11/2006
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Shih, Hung-Lin, Cheng, Po-Lun, Lin, Chun-An, Meng, Hsien-Liang, Liu, Che-Hung, Tang, Li-Yuen, Chiang, Jih-Shun, Fan, Ming-Chi
• Granted Patent: US 7,402,496 B2
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Claims

1. A method of fabricating a complementary metal-oxide-semiconductor device, comprising:

providing a substrate having an isolation structure dividing the substrate into a first active region and a second active region, wherein the first active region has a first gate structure, a first spacer structure and a first LDD formed therein and the second active region has a second gate structure, a second spacer structure and a second LDD formed therein;

forming a passivation layer conformally over the substrate, wherein the passivation layer comprises a carbon-containing oxynitride layer;

forming a photoresist layer on the passivation layer of the second active region;

performing an etching process by using the photoresist layer as a mask to remain a portion of the passivation layer on the first gate structure and the first spacer structure;

removing the photoresist layer;

removing a portion of the exposed substrate in the first active region by using the passivation layer as a mask to form a trench in the substrate;

filling an epitaxial material layer in the trench to serve as a first conductive source/drain (S/D) region;

removing the passivation layer; and

forming a doped region on the substrate in the second active region to serve as a second conductive S/D region.

2. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the carbon-containing oxynitride layer includes a bis(tert-butylamino)silane (BTBAS) oxide layer.

3. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 2, wherein the method for forming the bis(tert-butylamino)silane oxide layer comprises a low-pressure chemical-vapor deposition.

4. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 1, after the trench is formed, further comprises a step of performing a clean process.

5. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 4, before the clean process is performed and after the passivation layer is formed, further comprises a step of performing a thermal process on the passivation layer.

6. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 5, wherein the thermal process is performed at a temperature of about 750˜

800°

C.

7. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 5, wherein the thermal process is performed for about 30 seconds to 10 minutes.

8. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 5, wherein the thermal process is performed at a pressure of about 5˜

50 torr.

9. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 5, wherein a gas used in the thermal process is selected from a group consisting of helium, neon, argon, krypton, xenon and nitrogen.

10. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 1, after the doped region is formed, further comprising:

forming a stress layer in the second active region over the substrate, wherein the stress layer conformally covers the second gate structure, the second spacer structure and the doped region.

11. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 10, wherein the first conductive S/D region is a P-type S/D region and the epitaxial material layer is a SiGe layer and the stress layer is a tensile stress layer.

12. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 10, wherein the first conductive S/D region is an N-type S/D region and the epitaxial material layer is a SiC layer and the stress layer is a compressive stress layer.

13. A method of fabricating a complementary metal-oxide-semiconductor device, comprising:

providing a substrate having an isolation structure dividing the substrate into a first active region and a second active region, wherein the first active region has a first gate structure, a first spacer structure and a first LDD formed therein and the second active region has a second gate structure, a second spacer structure and a second LDD formed therein;

forming a first passivation layer to conformally cover the substrate, wherein the first passivation layer is a carbon-containing oxynitride layer;

forming a first photoresist layer on the substrate to cover the first passivation layer on the second active region;

performing an etching process by using the first photoresist layer as a mask to remain a portion of the first passivation layer on the first gate structure and the first spacer structure;

removing the first photoresist layer;

removing a part of the exposed substrate in the first active region by using the first passivation layer as a mask to form a first trench in the substrate;

filling a first epitaxial material layer in the first trench to serve as a first conductive S/D region;

removing the first passivation layer;

forming a second passivation layer to conformally cover the substrate, wherein the second passivation layer is a carbon-containing oxynitride layer;

forming a second photoresist layer on the substrate to cover the second passivation layer on the first active region;

performing an etching process by using the second photoresist layer as a mask to remain a portion of the second passivation layer on the second gate structure and the second spacer structure;

removing the second photoresist layer;

removing a portion of the exposed substrate in the second active region by using the second passivation layer as a mask to form a second trench in the substrate; and

filling a second epitaxial material layer in the first trench to serve as a second conductive S/D region.

14. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 13, wherein the carbon-containing oxynitride layer includes a bis(tert-butylamino)silane (BTBAS) oxide layer.

15. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 14, wherein the method for forming the bis(tert-butylamino)silane oxide layer comprises a low-pressure chemical-vapor deposition.

16. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 13 after the first trench is formed and/or the second trench is formed, further comprises a step of performing a clean process.

17. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 16, before the clean process is performed and after the first passivation layer and the second passivation layer are formed, further comprises a step of performing a thermal process on the first passivation layer and the second passivation layer.

18. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 17, wherein the thermal process is performed at a temperature of about 750˜

800°

C.

19. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 17, wherein the thermal process is performed for about 30 seconds to 10 minutes.

20. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 17, wherein the thermal process is performed at a pressure of about 5˜

50 torr.

21. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 17, wherein a gas used in the thermal process is selected from a group consisting of helium, neon, argon, krypton, xenon and nitrogen.

22. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 13, wherein the first conductive S/D region is a P-type S/D region, the second conductive S/D region is an N-type S/D region, the first epitaxial material layer is a SiGe layer, and the second epitaxial material layer is a SiC layer.

23. The method of fabricating a complementary metal-oxide-semiconductor device as claimed in claim 13, wherein the first conductive S/D region is an N-type S/D region, the second conductive S/D region is a P-type S/D region, the first epitaxial material layer is a SiC layer, and the second epitaxial material layer is a SiGe layer.

24. A complementary metal-oxide-semiconductor device, comprising:

a substrate having an isolation structure dividing the substrate into a first active region and a second active region;

a first gate structure, disposed on the substrate in the first active region;

a second gate structure, disposed on the substrate in the second active region;

a first spacer structure, disposed on a sidewall of the first gate structure;

a second spacer structure, disposed on a sidewall of the second gate structure;

a first LDD, disposed in the substrate at both sides of the first gate structure;

a second LDD, disposed on the substrate at both sides of the second gate structure;

an epitaxial material layer, disposed in the substrate in the first active region and located at a side of the first LDD to serve as a first conductive S/D region; and

a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer is a carbon-containing oxynitride layer.

25. The complementary metal-oxide-semiconductor device as claimed in claim 24, wherein the first conductive S/D region is a P-type S/D region and the epitaxial material layer is a SiGe layer.

26. The complementary metal-oxide-semiconductor device as claimed in claim 24, wherein the first conductive S/D region is an N-type S/D region and the epitaxial material layer is a SiC layer.

27. The complementary metal-oxide-semiconductor device as claimed in claim 24, wherein the carbon-containing oxynitride layer comprises a BTBAS oxide layer.

28. A complementary metal-oxide-semiconductor device, comprising:

a substrate having an isolation structure dividing the substrate into a first active region and a second active region;

a first gate structure, disposed on the substrate in the first active region;

a second gate structure, disposed on the substrate in the second active region;

a first spacer structure, disposed on a sidewall of the first gate structure;

a second spacer structure, disposed on a sidewall of the second gate structure;

a first LDD, disposed in the substrate at both sides of the first gate structure;

a second LDD, disposed on the substrate at both sides of the second gate structure;

a first epitaxial material layer, disposed in the substrate in the first active region and located at a side of the first LDD, so as to serve as a first conductive S/D region;

a second epitaxial material layer, disposed in the second active region and located at a side of the second LDD, so as to serve as a second conductive S/D region; and

a passivation layer, disposed on the second gate structure, the second spacer structure, and the second LDD and covering the first active region, wherein the passivation layer is a carbon-containing oxynitride layer.

29. The complementary metal-oxide-semiconductor device as claimed in claim 28, wherein the first conductive S/D region is a P-type S/D region, the second conductive S/D region is an N-type S/D region, the first epitaxial material layer is a SiGe layer, and the second epitaxial material layer is a SiC layer.

30. The complementary metal-oxide-semiconductor device as claimed in claim 28, wherein the first conductive S/D region is an N-type S/D region, the second conductive S/D region is a P-type S/D region, the first epitaxial material layer is a SiC layer, and the second epitaxial material layer is a SiGe layer.

31. The complementary metal-oxide-semiconductor device as claimed in claim 28, wherein the carbon-containing oxynitride layer comprises a BTBAS oxide layer.