Dielectric layers for metal lines in semiconductor chips

• US 20080061403A1
• Filed: 09/08/2006
• Published: 03/13/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Stamper, Anthony Kendall, Lu, Ning
• Granted Patent: US 7,598,166 B2
• Time in Patent Office: Days
• US Class Current: 257/635
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.

Claims

1. A semiconductor structure, comprising:

(a) a substrate;

(b) a first device and a second device each being on the substrate;

(c) a device cap dielectric layer on top of the first and second devices and on top of the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material;

(d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material;

(e) a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material; and

(f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers,

wherein the first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer, and

wherein a dielectric constant of the first dielectric material is less than a dielectric constant of the device cap dielectric material.

2. The structure of claim 1, wherein a dielectric constant of the second dielectric material is different from the dielectric constant of the first dielectric material.

3. The structure of claim 1, wherein a dielectric constant of the second dielectric material is the same as the dielectric constant of the first dielectric material.

4. The structure of claim 1, wherein the first dielectric material comprises a material selected from the group consisting of FSG (Fluorine-doped Silicate Glass), Bulk SiCOH (carbon-doped silicon oxides), and Porous SiCOH.

5. The structure of claim 1, wherein the first and second electrically conductive lines comprise copper.

6. The structure of claim 1, wherein the device cap dielectric layer comprises BPSG (Boro-Phospho-Silicate Glass).

7. The structure of claim 1, further comprising a first contact region and a second contact region each residing in the device cap dielectric material,

wherein the first contact region electrically couples the first electrically conductive line to the first device, and

wherein the second contact region electrically couples the second electrically conductive line to the second device.

8. The structure of claim 7, wherein the first and second contact regions comprise tungsten.

9. The structure of claim 1, further comprising a first cap layer, wherein the first cap layer is on top of and in direct physical contact with (i) the first and second electrically conductive lines and (ii) the second dielectric layer.

10. The structure of claim 9, wherein the first cap layer comprises a material selected from the group consisting of silicon carbide (SiC), silicon nitride (SiN), and silicon carbon nitride (SiCN).

11. The structure of claim 9, further comprising a second cap layer, wherein the second cap layer is sandwiched between the first and second dielectric layers.

12. The structure of claim 11, wherein the second cap layer comprises a material selected from the group consisting of silicon carbide (SiC), silicon nitride (SiN), and silicon carbon nitride (SiCN).

13. The structure of claim 1, wherein the first dielectric layer is in direct physical contact with the second dielectric layer.

14. A semiconductor structure fabrication method, comprising:

providing a semiconductor structure which includes;

(a) a substrate,

(b) a first device and a second device each being on the substrate,

(c) a device cap dielectric layer on top of the first and second devices and on top of the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material,

(d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material, and

(e) a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material; and

forming a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers,

wherein the first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer, and

wherein a dielectric constant of the first dielectric material is less than a dielectric constant of the device cap dielectric material.

15. The method of claim 14, wherein a dielectric constant of the second dielectric material is different from the dielectric constant of the first dielectric material.

16. The method of claim 14, wherein a dielectric constant of the second dielectric material is the same as the dielectric constant of the first dielectric material.

17. The method of claim 14, wherein the first dielectric material comprises a material selected from the group consisting of FSG (Fluorine-doped Silicate Glass), Bulk SiCOH (carbon-doped silicon oxides), and Porous SiCOH.

18. The method of claim 14, wherein the semiconductor structure further includes a first contact region and a second contact region each residing in the device cap dielectric material,

wherein the first contact region electrically couples the first electrically conductive line to the first device, and

wherein the second contact region electrically couples the second electrically conductive line to the second device.

19. The method of claim 14, further comprising, after said forming the first and second electrically conductive lines, forming a first cap layer, wherein the first cap layer is on top of and in direct physical contact with (i) the first and second electrically conductive lines and (ii) the second dielectric layer.

20. The method of claim 19, wherein the semiconductor structure further includes a second cap layer, wherein the second cap layer is sandwiched between the first and second dielectric layers.