PACKAGING STRUCTURE AND FABRICATING METHOD THEREOF

• US 20080061427A1
• Filed: 04/11/2007
• Published: 03/13/2008
• Est. Priority Date: 09/11/2006
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chiang, Chia-Wen
• Granted Patent: US 7,638,875 B2
• Time in Patent Office: Days
• US Class Current: 257/700
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A packaging structure including an interposer structure, a first electronic component, and a second electronic component is provided. The interposer structure includes a first dielectric layer, a plurality of contacts, a capacitive element, and an interconnection. The contacts are disposed on the upper and lower surfaces of the first dielectric layer and the capacitive element, which comprises two conductive layers and a second dielectric layer located among the layers, is embedded into the first dielectric layer. And the interconnection is embedded into the first dielectric layer, while the capacitive element electrically connects to the corresponding contacts through the interconnection. The first and the second electronic components are disposed respectively on the upper and bottom sides of the interposer structure and electrically connected to the corresponding contacts.

Claims

1. A packaging structure, comprising:

an interposer structure, including;

a first dielectric layer;

a plurality of contacts, which are disposed on the upper and lower surfaces of the first dielectric layer;

a capacitive element, which is embedded into the first dielectric layer and the capacitive element comprises two conductive layers and a second dielectric layer among them;

an interconnection, which is embedded into the first dielectric layer and the capacitive element electrically connects to the corresponding contacts through the interconnection; and

a first electronic component and a second electronic component, which are electrically connected to the corresponding contacts and respectively disposed on the upper and lower sides of the interposer structure.

2. The packaging structure as described in claim 1, wherein the permittivity of the first dielectric layer is smaller than that of the second dielectric layer.

3. The packaging structure as described in claim 1, further comprising an inductive element embedded into the first dielectric layer.

4. The packaging structure as described in claim 3, wherein the inductive element is disposed surrounding the capacitive element.

5. The packaging structure as described in claim 1, wherein the capacitive element further includes a barrier layer, which is disposed between one of the conductive layers and the second dielectric layer.

6. The packaging structure as described in claim 5, wherein the material of the barrier layer includes titanium (Ti), platinum (Pt), or silver (Ag).

7. The packaging structure as described in claim 1, wherein the material of the second dielectric layer includes ceramic.

8. The packaging structure as described in claim 7, wherein the material of the second dielectric layer includes barium titanate (BaTiO3) or strontium titanate (SrTiO3).

9. The packaging structure as described in claim 1, wherein the material of the first dielectric layer includes benzocyclobutene (BCB) or polyimide (PI).

10. The packaging structure as described in claim 1, wherein the interposer structure further includes a resistive module, which is embedded into the first dielectric layer and stacked up with the capacitive element, and the resistive module is electrically connected to the corresponding contacts through the interconnection.

11. The packaging structure as described in claim 10, wherein the resistive module comprises:

a substrate; and

a resistive thin film, which is disposed on the substrate and electrically connects to the interconnection.

12. The packaging structure as described in claim 11, wherein the resistive module further comprises:

a plurality of electrodes, which are disposed on the substrate and the resistive thin film is connected to the interconnection through the electrodes; and

a passivation layer, which is disposed on the substrate and covers the resistive thin film and the electrodes.

13. The packaging structure as described in claim 11, wherein the material of the substrate is ceramic.

14. The packaging structure as described in claim 1, wherein the first electronic component is a semiconductor chip or a wafer.

15. The packaging structure as described in claim 1, wherein the second electronic component is a semiconductor chip or a wafer.

16. A fabricating method of packaging structure, comprising:

forming a capacitive element;

forming a first dielectric layer on a first electronic component by performing a build-up process, forming an interconnection in the first dielectric layer, and forming a plurality of contacts on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection; and

disposing a second electronic component on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts.

17. The fabricating method of the packaging structure as described in claim 16, wherein the capacitive element comprises two conductive layers and a second dielectric layer located among them, in which the permittivity of the first dielectric layer is smaller than that of the second dielectric layer.

18. The fabricating method of the packaging structure as described in claim 16, further comprising forming an inductive element at the same time of fabricating the interconnection and the inductive element is electrically connected to the corresponding contacts through the interconnection.

19. The fabricating method of the packaging structure as described in claim 18, wherein the inductive element is disposed surrounding the capacitive element.

20. The fabricating method of the packaging structure as described in claim 16, wherein the steps of forming the capacitive element includes:

providing a metal film;

coating a dielectric material on the metal film; and

forming an electrode layer on the dielectric material.

21. The fabricating method of the packaging structure as described in claim 20, wherein the dielectric material includes ceramic slurry.

22. The fabricating method of the packaging structure as described in claim 20, further comprising performing a thermal treatment process to the dielectric material after coating the same.

23. The fabricating method of the packaging structure as described in claim 20, further comprising forming a barrier layer on the metal film before coating the dielectric material.

24. The fabricating method of the packaging structure as described in claim 20, wherein the finished capacitive element is trimmed into a certain size after the electrode layer is formed.

25. The fabricating method of the packaging structure as described in claim 20, further comprising performing an etching process to the capacitive element to define the surface area thereof after the capacitive element is embedded into the first dielectric layer.

26. The fabricating method of the packaging structure as described in claim 16, further comprising providing a resistive module at the same time of fabricating the interconnection, and making the resistive module and the capacitive element stacked up with each other and to be embedded into the first dielectric layer, wherein the resistive module is electrically connected to the corresponding contacts through the interconnection.

27. The fabricating method of the packaging structure as described in claim 26, wherein the capacitive element and the resistive module are stacked up with each other first, and then being embedded into the first dielectric layer together.

28. The fabricating method of the packaging structure as described in claim 26, wherein the steps of fabricating the resistive module includes:

providing a substrate; and

forming a resistive thin film on the substrate.

29. The fabricating method of the packaging structure as described in claim 28, wherein the steps of fabricating the resistive module further includes:

forming a plurality of electrodes on the substrate, wherein the resistive thin film is electrically connected with the electrodes; and

forming a passivation layer on the substrate to cover the electrodes and the resistive thin film.

30. The fabricating method of the packaging structure as described in claim 16, wherein the first electronic component is a semiconductor chip or a wafer.

31. The fabricating method of the packaging structure as described in claim 16, wherein the second electronic component is a semiconductor chip or a wafer.