LOW DIELECTRIC CONSTANT FILM PRODUCED FROM SILICON COMPOUNDS COMPRISING SILICON-CARBON BOND

• US 20080061439A1
• Filed: 10/23/2007
• Published: 03/13/2008
• Est. Priority Date: 02/11/1998
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Cheung, David, Jeng, Shin-Puu, Yau, Wai-Fan, Liu, Kuowei, Yu, Yung-Cheng
• Application Number:
  US11/877,488
• Publication Number:
  US 20080061439A1
• Time in Patent Office: Days
• US Class Current: 257/759
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH₃SiH₃, and N₂O.

Claims

1. An integrated circuit structure, comprising:

regions of dielectric material separating regions of conductive material within a layer, wherein the regions of dielectric material comprise;

a first dielectric material comprising a porous low k dielectric material; and

a second dielectric material comprising silicon, oxygen, and carbon, wherein the second dielectric material forms a low k lining layer between the first dielectric material and the regions of conductive material.

2. The integrated circuit structure of claim 1, wherein the first dielectric material is a spin-on porous silicon oxide.

3. The integrated circuit structure of claim 1, further comprising a cap layer on the first dielectric material, the cap layer comprising the second dielectric material.

4. An integrated circuit structure, comprising:

regions of dielectric material separating regions of conductive material, wherein the regions of dielectric material comprise;

a first dielectric material comprising a porous low k dielectric material;

a second dielectric material comprising silicon, oxygen, and carbon, wherein the second dielectric material forms a cap layer on the first dielectric material.

5. The integrated circuit structure of claim 4, wherein the first dielectric material is a spin-on porous silicon oxide.

6. The integrated circuit structure of claim 4, further comprising a lining layer between the first dielectric material and the regions of conductive material, wherein the lining layer comprises the second dielectric material.