Reducing Common Mode Noise of Power Factor Correction Converters Using General Balance Concept

• US 20080061748A1
• Filed: 09/13/2006
• Published: 03/13/2008
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Virginia Tech Intellectual Properties, Inc. (Virginia Polytechnic Institute and State University)
• Original Assignee: Virginia Tech Intellectual Properties, Inc. (Virginia Polytechnic Institute and State University)
• Inventors: Wang, Shuo, Lee, Fred, Kong, Pengju
• Granted Patent: US 7,804,281 B2
• Time in Patent Office: Days
• US Class Current: 323/222
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

Common mode (CM) noise is substantially canceled in a switching power supply circuit such as a boost converter by providing a split inductor and analyzing the switching power supply circuit as a bridge circuit formed of the switch, portions of the split inductor and parasitic capacitances of respective portions of the power supply circuit. The bridge can then be balanced by addition of capacitance in parallel with the parasitic capacitance of a respective portion of the power supply circuit or dividing the split inductor such that a ratio of inductances of respective portions of the split inductor approximates a ratio of parasitic capacitances of the respective power supply circuit portions which may be measured or otherwise empirically determined. CM noise reduction of up to 40 db can be achieved without symmetric circuit design, addition of circuit elements or complex filtering having added cost, space requirements and power losses. Further, such a reduction in common mode noise allows simple EMI filtering arrangements to be employed further reducing cost and space requirements for the power supply circuit.

Claims

1. A power supply circuit comprising

an inductor configured in two portions,

a switch controlling conduction through said inductor,

circuit portions having respective parasitic capacitances, and

means for approximately balancing currents in said two portions of said inductor.

2. A power supply circuit as recited in claim 1 wherein the inductances of said two portions of said inductor are equal and wherein said power supply circuit includes a capacitance in parallel with said parasitic capacitance of one of said circuit portions.

3. A power supply circuit as recited in claim 2, wherein said portions of said inductor are inductively coupled.

4. A power supply circuit as recited in claim 1, wherein said inductor is divided into portions such that a ratio of the inductances of said two portions approximates a ration of said respective parasitic capacitances.

5. A power supply circuit as recited in claim 4, wherein said portions of said inductor are inductively coupled.

6. A method of cancelling common mode noise in a power supply circuit including a switch, said method including steps of

determining parasitic capacitances of circuit portions forming respective portions of a bridge network in combination with said switch and respective portions of an inductor, and

approximately balancing said bridge network.

7. A method as recited in claim 6, wherein said determining step is performed by measurement.

8. A method as recited in claim 7, wherein said step of approximately balancing said bridge network includes a step of

adding capacitance in parallel with a said parasitic capacitance.

9. A method as recited in claim 8 wherein said step of adding capacitance is performed by connecting a capacitor in parallel with said parasitic capacitance.

10. A method as recited in claim 7 wherein said step of approximately balancing said bridge network includes a step of

dividing said inductor into portions such that a ratio of said inductances of respective portion of said inductor approximates a ratio of said parasitic capacitances.

11. A method as recited in claim 10, wherein said portions of said inductor are inductively coupled.

12. A method as recited in claim 6, wherein said step of approximately balancing said bridge network includes a step of

adding capacitance in parallel with a said parasitic capacitance.

13. A method as recited in claim 12 wherein said step of adding capacitance is performed by connecting a capacitor in parallel with said parasitic capacitance.

14. A method as recited in claim 6 wherein said step of approximately balancing said bridge network includes a step of

dividing said inductor into portions such that a ratio of said inductances of respective portion of said inductor approximates a ratio of said parasitic capacitances.

15. A method as recited in claim 14, wherein said portions of said inductor are inductively coupled.