CONFIGURABLE IC'S WITH LOGIC RESOURCES WITH OFFSET CONNECTIONS

• US 20080061823A1
• Filed: 09/17/2007
• Published: 03/13/2008
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Brad Hutchings, Herman Schmit, Randy Huang, Steve Teig
• Inventors: Teig, Steven, Hutchings, Brad, Schmit, Herman, Huang, Randy
• Granted Patent: US 7,839,166 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. Also, in some embodiments, each particular tile further has a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile. At least a first input select circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, where the direction connection is for supplying a signal to the first input select circuit. In some embodiments, several logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. In some embodiments, several input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Claims

1-33. -33. (canceled)

34. A configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable titles arranged in a tile arrangement,

each configurable tile comprising a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

wherein at least a first logic circuit of a first tile comprises at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement; and

wherein said direct connection comprises at least one intervening buffer circuit.