Detecting voltage glitches

• US 20080061843A1
• Filed: 09/11/2006
• Published: 03/13/2008
• Est. Priority Date: 09/11/2006
• Status: Abandoned Application

• Current Assignee: Inside Secure SA
• Original Assignee: Inside Secure SA
• Inventors: Yanci, Asier Goikoetxea
• Application Number:
  US11/519,382
• Publication Number:
  US 20080061843A1
• Time in Patent Office: Days
• US Class Current: 327/78
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13

Abstract

In some implementations, an apparatus includes a filter circuit that receives an input signal and generates in response a filtered signal; and a comparison circuit that receives the input signal and the filtered signal, and outputs in response a comparison output signal having a first level when a magnitude of the filtered signal is less than or substantially equal to a magnitude of the input signal and a second level when the magnitude of the filtered signal is greater than the magnitude of the input signal. The filter circuit can be configured to generate the filtered signal including applying a first transfer function to the input signal when the magnitude of the input signal is substantially constant or increasing, and applying a second transfer function to the input signal when the magnitude of the input signal is decreasing.

Claims

1. An apparatus comprising:

a filter circuit that receives an input signal and generates in response a filtered signal; and

a comparison circuit that receives the input signal and the filtered signal, and outputs in response a comparison output signal having a first level when a magnitude of the filtered signal is less than or substantially equal to a magnitude of the input signal and a second level when the magnitude of the filtered signal is greater than the magnitude of the input signal;

wherein the filter circuit is configured to generate the filtered signal including applying a first transfer function to the input signal when the magnitude of the input signal is substantially constant or increasing, and applying a second transfer function to the input signal when the magnitude of the input signal is decreasing.

2. The apparatus of claim 1, wherein the input signal is a voltage signal corresponding to a voltage supply rail of a system.

3. The apparatus of claim 2, wherein the filter circuit and the comparison circuit are configured to detect a voltage glitch on the voltage supply rail.

4. The apparatus of claim 3, wherein the filter circuit and the comparison circuit are configured to detect a voltage glitch on the voltage supply rail that causes, within a predetermined time period, a level of the voltage supply rail to begin at substantially a nominal voltage level, rise to a maximum voltage level, and settle back to substantially the nominal voltage level.

5. The apparatus of claim 4, wherein the predetermined time period is substantially 10 nanoseconds or less.

6. The apparatus of claim 4, wherein the predetermined time period is substantially 100 nanoseconds or less.

7. The apparatus of claim 1, wherein the filter circuit comprises:

a complementary metal-oxide semiconductor (CMOS) inverter having a voltage supply input, a voltage reference input, a logic input and a logic output; and

a diode having an anode terminal and a cathode terminal;

wherein the voltage supply input of the CMOS inverter is coupled to the cathode terminal of the diode, the anode terminal of the diode is coupled to the input signal, the voltage reference input of the CMOS inverter is coupled to a ground reference of the system, the logic input of the CMOS inverter is coupled to a voltage level substantially corresponding to the ground reference of the system, and the logic output of the CMOS inverter provides the filtered signal.

8. The apparatus of claim 7, wherein the first transfer function corresponds to a charging function of parasitic capacitance in the CMOS inverter and current through a portion of the CMOS inverter and the diode when the diode is in a forward-biased state.

9. The apparatus of claim 7, wherein the second transfer function corresponds to a discharging function of parasitic capacitance in the CMOS inverter and current through a portion of the CMOS inverter and the diode when the diode is in a reverse-biased state.

10. The apparatus of claim 7, wherein the comparison circuit comprises a comparator having a positive input, a negative input and a comparator output;

wherein, the positive terminal is coupled to the input signal, the negative terminal is coupled to the logic output of the CMOS inverter and the comparator output provides the comparison output signal.

11. The apparatus of claim 1, further comprising an alarm circuit that receives the comparison output signal and outputs in response an alarm output signal having a first mode or a second mode, wherein the alarm circuit is configured to initially output the alarm output signal in the first mode and output the alarm signal in the second mode when the comparison output signal transitions to the second level.

12. The apparatus of claim 11, wherein the alarm circuit comprises at least one of a latch;

a set-reset flip-flop;

or a circuit configured to store a value, receive an input, and provide an output based on the input relative to the stored value.

13. The apparatus of claim 11, wherein the alarm circuit is configured to persistently output the alarm signal in the second mode once the comparison output signal transitions to the second level.

14. The apparatus of claim 11, further comprising a reset circuit that is configured to cause the alarm circuit to output the alarm signal in the first mode following a reset condition.

15. The apparatus of claim 1, further comprising a protective circuit that is activated in response to the alarm circuit outputting the alarm signal in the second mode.

16. The apparatus of claim 15, wherein the protective circuit comprises a reset circuit that resets at least a portion of another circuit that is coupled to the input signal.

17. The apparatus of claim 15, wherein the protective circuit comprises a power control circuit that powers down at least a portion of another circuit that is coupled to the input signal.

18. A method comprising:

receiving an input signal;

determining if a magnitude of the input signal is increasing or remaining substantially constant, or decreasing;

generating a filtered signal including applying a first transfer function to the input signal if the magnitude is increasing or remaining substantially constant, and applying a second, different transfer function to the input signal if the magnitude is decreasing; and

comparing the filtered signal and the received input signal and providing an output signal having a first level if a magnitude of the filtered signal is less than or equal to the magnitude of the input signal and a second level if the magnitude of the filtered signal is greater than the magnitude of the input signal.

19. The method of claim 18, further comprising latching the value of the output signal when the output signal transitions from the first level to the second level.

20. The method of claim 18, wherein providing an output signal having the second level comprises detecting a voltage glitch on the input signal.

21. The method of claim 20, wherein detecting a voltage glitch on the input signal comprises detecting a voltage glitch that causes, within a predetermined time period, a level of the input signal to begin at substantially a nominal level, rise to a maximum voltage level, and settle back to substantially the nominal voltage level.

22. The method of claim 21, wherein the predetermined time period is substantially 10 nanoseconds or less.

23. The method of claim 21, wherein the predetermined time period is substantially 100 nanoseconds or less.

24. A method comprising:

generating an input signal corresponding to a level of a supply voltage of a device;

determining if the level is increasing or remaining substantially constant, or decreasing;

generating a filtered signal including applying a first transfer function to the input signal if the level is increasing or remaining substantially constant, and applying a second, different transfer function to the input signal if the level is decreasing; and

asserting an alarm signal if a magnitude of the filtered signal exceeds a magnitude of the input signal.

25. The method of claim 24, further comprising activating a protective circuit if the magnitude of the filtered signal exceeds the magnitude of the input signal.

26. The method of claim 25, wherein activating the protective circuit comprises resetting at least a portion of the device.

27. The method of claim 25, wherein activating the protective circuit comprises powering down at least a portion of the device.

28. The method of claim 24, further comprising comparing the filtered signal and the input signal to determine if the magnitude of the filtered signal exceeds the magnitude of the input signal.