MULTI-LOOP PHASE LOCKED LOOP CIRCUIT

• US 20080061888A1
• Filed: 08/27/2007
• Published: 03/13/2008
• Est. Priority Date: 09/07/2006
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ren-Chieh
• Granted Patent: US 7,622,996 B2
• Time in Patent Office: Days
• US Class Current: 331/11
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.

Claims

1. A multi-loop phase locked loop apparatus, comprising:

a first loop, comprising;

a first phase/frequency detector, for detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal; and

a first charge pump, coupled to the first phase/frequency detector, for generating a first control current according to the first difference signal;

a second loop, comprising;

a second phase/frequency detector, for detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal; and

a second charge pump, coupled to the second phase/frequency detector, for generating a second control current according to the second difference signal;

a loop filter, coupled to the first charge pump and the second charge pump, for generating a control signal;

a voltage control oscillator, coupled to the loop filter, for generating an oscillating signal according to the control signal;

a first frequency divider, coupled to the voltage control oscillator and the first phase/frequency detector, for frequency-dividing the oscillating signal to generate the first feedback clock signal;

a second frequency divider, coupled to the voltage control oscillator and the second phase/frequency detector, for frequency-dividing the oscillating signal to generate the second feedback clock signal; and

a control circuit, coupled to the first loop and the second loop, for switching between the first loop and the second loop to generate the control signal according to at least one of the first control current, the second control current and the control signal.

2. The multi-loop phase locked loop apparatus of claim 1, wherein the frequency of the second reference clock signal is higher than that of the first reference clock signal.

3. The multi-loop phase locked loop apparatus of claim 2, wherein the control circuit turns off the second loop and turns on the first loop after the multi-loop phase locked loop apparatus is locked to the second reference clock signal.

4. The multi-loop phase locked loop apparatus of claim 1, wherein the frequency of the second reference clock signal is at least triple that of the first reference clock signal.

5. The multi-loop phase locked loop apparatus of claim 1, wherein the second reference clock signal is generated by a PLL circuit according to the first reference clock signal.

6. The multi-loop phase locked loop apparatus of claim 1, further comprising a third loop, wherein the third loop comprises:

a third phase/frequency detector, for detecting the difference between a third feedback clock signal and a third reference clock signal to output a third difference signal; and

a third charge pump, coupled to the third phase/frequency detector, for generating a third control current according to the third difference signal.

7. The multi-loop phase locked loop apparatus of claim 1, further comprising a computing unit, for computing a time parameter, wherein the control circuit switches the original used loop to the other loop if the time parameter reaches a predetermined value.

8. The multi-loop phase locked loop apparatus of claim 1, further comprising a monitoring circuit, for monitoring the value of the first control current and the second control current or, wherein if the control signal is stable, the control circuit switches the first loop or the second loop.

9. A phase locking method, comprising:

detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal;

generating a first control current according to the first difference signal;

detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal;

generating a second control current according to the second difference signal;

generating a control signal according to at least one of the first control current and the second control current; and

generating a first oscillating signal according to the control signal.

10. The phase locking method of claim 9, further comprising:

frequency-dividing the first oscillating signal to generate the first feedback clock signal; and

frequency-dividing the second oscillating signal to generate the second feedback clock signal.

11. The phase locking method of claim 10, wherein the frequency of the second reference clock signal is higher than that of the first reference clock signal.

12. The phase locking method of claim 9, further comprising utilizing the first reference clock signal to generate the second oscillating signal after the first oscillating signal is locked to the second reference clock signal.

13. The phase locking method of claim 9, wherein the frequency of the second reference clock signal is at least triple that of the first reference clock signal.

14. The phase locking method of claim 9, wherein the second reference clock signal is generated by a PLL circuit according to the first reference clock signal.

15. The phase locking method of claim 9, wherein the first reference clock signal is generated by an oscillating crystal.

16. The phase locking method of claim 9, further comprising:

detecting the difference between a third feedback clock signal and a third reference clock signal to output a third difference signal;

generating a third control current according to the third difference signal; and

generating the control signal according to al least one of the first control current, the second control current, and the third control current.

17. A multi-loop phase locked loop apparatus, comprising:

a feedback clock signal generating module, for generating a first feedback clock signal and a second feedback clock signal;

a first loop, for detecting the difference between the first feedback clock signal and a first reference clock to generate a first loop signal;

a second loop, for detecting the difference between the second feedback clock signal and a second reference clock to generate a second loop signal; and

a control unit, for choosing one of the first loop signal and the second loop signal to be the feedback clock signal, wherein the feedback clock signal generating module generates the first feedback clock signal and the second feedback clock signal according to the feedback clock signal generating module.

18. The multi-loop phase locked loop apparatus of claim 17, further comprising a loop filter, coupled between the first loop and the feedback clock signal generating module and coupled between the second loop and the feedback clock signal generating module.

19. The multi-loop phase locked loop apparatus of claim 17, wherein the first loop comprises a first phase/frequency detector and a first charge pump, and the second loop comprises a second phase/frequency detector and a second charge pump.

20. The multi-loop phase locked loop apparatus of claim 17, wherein the feedback clock signal generating module comprises:

a voltage control oscillator, for generating a first oscillating signal and a second oscillating signal;

a first frequency divider, coupled to the voltage control oscillator and the first loop, for generating the first feedback clock signal according to the first oscillating signal; and

a second frequency divider, coupled to the voltage control oscillator and the second loop, for generating the second feedback clock signal according to the second oscillating signal.

21. The multi-loop phase locked loop apparatus of claim 17, wherein the feedback clock signal generating module comprises:

a voltage control oscillator, for generating an oscillating signal;

a first frequency divider, coupled to the first loop, for generating the first feedback clock signal according to the second feedback clock signal; and

a second frequency divider, coupled to the first frequency divider, the voltage control oscillator and the second loop, for generating the second feedback clock signal according to the oscillating signal.

22. The multi-loop phase locked loop apparatus of claim 17, wherein the feedback clock signal generating module comprises:

a voltage control oscillator, for generating a first oscillating signal and a second oscillating signal;

a two output frequency divider, coupled to the voltage control oscillator, the first loop and the second loop, for generating the first feedback clock signal according to the first oscillating signal or generating the second feedback clock signal according to the first oscillating signal.

23. The multi-loop phase locked loop apparatus of claim 17, being included in a UWB (Ultra Wideband) apparatus.

24. The multi-loop phase locked loop apparatus of claim 17, wherein the control circuit is a logic circuit.

25. The multi-loop phase locked loop apparatus of claim 24, wherein the control circuit is an AND gate or a switch.

26. The multi-loop phase locked loop apparatus of claim 17, further comprising a computing unit, for computing a time parameter, wherein the control circuit switches the original used loop to the other loop if the time parameter reaches a predetermined value.

27. The multi-loop phase locked loop apparatus of claim 17, further comprising a monitoring circuit, for monitoring the value of the first control current and the second control current or, if the control signal is stable, the control circuit switches the first loop or the second loop.