MULTI-LOOP PHASE LOCKED LOOP CIRCUIT
First Claim
1. A multi-loop phase locked loop apparatus, comprising:
- a first loop, comprising;
a first phase/frequency detector, for detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal; and
a first charge pump, coupled to the first phase/frequency detector, for generating a first control current according to the first difference signal;
a second loop, comprising;
a second phase/frequency detector, for detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal; and
a second charge pump, coupled to the second phase/frequency detector, for generating a second control current according to the second difference signal;
a loop filter, coupled to the first charge pump and the second charge pump, for generating a control signal;
a voltage control oscillator, coupled to the loop filter, for generating an oscillating signal according to the control signal;
a first frequency divider, coupled to the voltage control oscillator and the first phase/frequency detector, for frequency-dividing the oscillating signal to generate the first feedback clock signal;
a second frequency divider, coupled to the voltage control oscillator and the second phase/frequency detector, for frequency-dividing the oscillating signal to generate the second feedback clock signal; and
a control circuit, coupled to the first loop and the second loop, for switching between the first loop and the second loop to generate the control signal according to at least one of the first control current, the second control current and the control signal.
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Accused Products
Abstract
Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.
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Citations
27 Claims
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1. A multi-loop phase locked loop apparatus, comprising:
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a first loop, comprising; a first phase/frequency detector, for detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal; and a first charge pump, coupled to the first phase/frequency detector, for generating a first control current according to the first difference signal; a second loop, comprising; a second phase/frequency detector, for detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal; and a second charge pump, coupled to the second phase/frequency detector, for generating a second control current according to the second difference signal; a loop filter, coupled to the first charge pump and the second charge pump, for generating a control signal; a voltage control oscillator, coupled to the loop filter, for generating an oscillating signal according to the control signal; a first frequency divider, coupled to the voltage control oscillator and the first phase/frequency detector, for frequency-dividing the oscillating signal to generate the first feedback clock signal; a second frequency divider, coupled to the voltage control oscillator and the second phase/frequency detector, for frequency-dividing the oscillating signal to generate the second feedback clock signal; and a control circuit, coupled to the first loop and the second loop, for switching between the first loop and the second loop to generate the control signal according to at least one of the first control current, the second control current and the control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A phase locking method, comprising:
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detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal; generating a first control current according to the first difference signal; detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal; generating a second control current according to the second difference signal; generating a control signal according to at least one of the first control current and the second control current; and generating a first oscillating signal according to the control signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A multi-loop phase locked loop apparatus, comprising:
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a feedback clock signal generating module, for generating a first feedback clock signal and a second feedback clock signal; a first loop, for detecting the difference between the first feedback clock signal and a first reference clock to generate a first loop signal; a second loop, for detecting the difference between the second feedback clock signal and a second reference clock to generate a second loop signal; and a control unit, for choosing one of the first loop signal and the second loop signal to be the feedback clock signal, wherein the feedback clock signal generating module generates the first feedback clock signal and the second feedback clock signal according to the feedback clock signal generating module. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification