FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME

• US 20080062760A1
• Filed: 06/13/2007
• Published: 03/13/2008
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 7,593,259 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

Claims

1. A Flash memory device comprising:

a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable to have a program threshold voltage in the erase voltage domain;

row control logic for selectively driving a wordline connected to a gate terminal of a memory cell with one of a positive voltage and a negative voltage during program verify and read operations;

2. The Flash memory device of claim 1, further including a positive voltage generator for providing a positive voltage, and a negative voltage generator for providing a negative voltage.

3. The Flash memory device of claim 1, wherein each memory cell is programmable to have the program threshold voltage in a program voltage domain.

4. The Flash memory device of claim 1, wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.

5. The Flash memory device of claim 4, wherein each memory cell is programmable to store two bits of data corresponding to first, second, third and fourth threshold voltages.

6. The Flash memory device of claim 5, wherein the first threshold voltage and the second threshold voltage are in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage are in the program voltage domain.

7. The Flash memory device of claim 6, wherein the first threshold voltage corresponds to the erase threshold voltage.

9. The method of claim 7, wherein the first voltage level is a positive voltage.

10. The method of claim 7, wherein the erased memory cells have an erased threshold voltage in an erase voltage domain and the reference voltage is in the erase voltage domain.

11. The method of claim 10, wherein the reference voltage is greater than the erased threshold voltage and less than a programmed threshold voltage in the erase voltage domain.

12. The method of claim 10, further including erasing the memory cells if no voltage level change is sensed in the bitline.

13. The method of claim 12, further including repeating the steps of precharging, applying and sensing after the step of erasing the memory cells.

8. A method for verifying a threshold voltage of memory cells configured in a NAND string, the method comprising:

precharging a bitline coupled to the NAND string to a first voltage level;

applying a reference voltage to all wordlines connected to the erased memory cells of the NAND string for coupling the bitline to a second voltage level; and

,

sensing a voltage level change in the bitline.

14. A method for programming a Flash memory cell initially erased to have a first threshold voltage in an erase voltage domain, the method comprising:

changing the first threshold voltage of the Flash memory cell to a second threshold voltage, the second threshold voltage being in the erase voltage domain.

15. The method of claim 14, wherein the step of changing includes:

biasing a bitline connected to the Flash memory cell to a programming voltage level; and

driving a wordline connected to the Flash memory cell with a predetermined number of pulses, each pulse having a predetermined step size.

16. The method of claim 14, further including verifying the second threshold voltage and repeating the step of changing if the Flash memory cell does not have the second threshold voltage.

17. The method of claim 16, wherein the step of verifying includes

precharging a bitline connected to the Flash memory cell to a first voltage level,

driving a wordline connected to the Flash memory cell with a reference voltage in the erase voltage domain, and

sensing a voltage level change in the bitline.

18. The method of claim 17, wherein the reference voltage is greater than the first threshold voltage and less than the second threshold voltage.

19. The method of claim 15, wherein the Flash memory cell and a plurality of Flash memory cells form a NAND string, and the step of driving further includes driving wordlines connected to the plurality of Flash memory cells with a pass voltage.

20. A method for reading a Flash memory cell programmable to have an erase voltage domain threshold voltage or a programming domain threshold voltage, the method comprising:

determining one of an erase threshold voltage and the erase voltage domain threshold voltage by applying an erase voltage domain reference voltage to a gate terminal of the Flash memory cell and sensing a bitline voltage connected to the Flash memory cell;

storing a logical state of the Flash memory cell in response to the step of determining one of an erase threshold voltage and the erase voltage domain threshold voltage;

determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage by applying another reference voltage to the gate terminal and sensing the bitline voltage connected to the Flash memory cell; and

updating the logical state in response to the step of determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage.

21. A Flash memory device comprising:

a memory array having memory cells, each memory cell erasable to have a threshold voltage in an erase voltage domain, and programmable to have at least one threshold voltage level in the erase voltage domain and at least another threshold voltage in a program voltage domain.

22. The Flash memory device of claim 21, wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.

23. The Flash memory device of claim 21, wherein each memory cell is programmable to store a plurality of bits of data corresponding to first, second, third and fourth threshold voltages.

24. The Flash memory device of claim 23, wherein the first threshold voltage and the second threshold voltage are in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage are in the program voltage domain.

25. The Flash memory device of claim 21, wherein the erase voltage domain includes threshold voltages that are positive and the program voltage domain includes threshold voltages that are negative.

26. The Flash memory device of claim 21, further including row control logic for selectively driving a wordline with a negative voltage and positive voltage in response to a row address.

27. The Flash memory device of claim 26, further including a first voltage generator for providing the positive voltage and a second voltage generator for providing the negative voltage.

28. The Flash memory device of claim 27, wherein the row control logic further comprises:

a row decoder for receiving the positive voltage and the negative voltage, the row decoder providing row signals in response to the row address, and

a wordline driver for passing the row signals in response to an enable signal.

29. The Flash memory device of claim 28, wherein the row control logic further comprises:

a block decoder for providing the enable signal in response to a block address, the enable signal having one of the positive voltage and the negative voltage.