MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE

• US 20080062807A1
• Filed: 09/11/2007
• Published: 03/13/2008
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Chad Bellows, Frederick Ware, Lawrence Lai, Wayne Richardson
• Original Assignee: Chad Bellows, Frederick Ware, Lawrence Lai, Wayne Richardson
• Inventors: Bellows, Chad, Ware, Frederick, Lai, Lawrence, Richardson, Wayne
• Granted Patent: US 7,505,356 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Claims

1. An integrated circuit memory device, comprising:

an interface;

a storage array having a row of storage cells; and

a column decoder to access the row of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;

during the first mode of operation, the row of storage cells is accessible from the interface in response to a first column address; and

during the second mode of operation, a first plurality of storage cells in the row of storage cells is accessible from the interface in response to a second column address and a second plurality of storage cells in the row of storage cells is accessible from the interface in response to a third column address, wherein the first plurality of storage cells and the second plurality of storage cells are concurrently accessible from the interface.