Compensation for gain imbalance, phase imbalance and DC offsets in a transmitter

• US 20080063113A1
• Filed: 04/25/2007
• Published: 03/13/2008
• Est. Priority Date: 09/07/2006
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Gao, Wei, Shih, Didmin
• Granted Patent: US 7,881,402 B2
• Time in Patent Office: Days
• US Class Current: 375/296
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 2027/0018 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only

Abstract

A method for correcting gain imbalance error, phase imbalance error and DC offset errors in a transmitter having an OFDM-based I/Q modulator is disclosed. The method employs a compensator prior to the I/Q-modulator to compensate for the gain and phase imbalance and DC offset. The compensator is efficiently updated with the estimated values of gain and phase imbalance and DC offsets obtained by performing the DFT operation in the digital baseband domain while sending a pair of orthogonal test tones to the modulator'"'"'s inputs from a digital baseband chip, then down converting the RF modulated signal through a nonlinear device and a bandpass filter to a baseband signal, and finally sampling it using an A/D. The delay mismatch, which is mainly generated by lowpass filters between the I and Q branches, is also minimized in this method.

Claims

1. A method of compensating for one or more errors in a transmitter, wherein the transmitter includes a compensator circuit, said quadrature modulator and a feedback path, the method comprising:

(a) supplying an orthogonal pair of tones as calibration signals to the compensator circuit;

(b) adjusting a delay value of a delay unit in the feedback path in order to approximate the condition that a sum of a first phase lag corresponding to the delay value plus a second phase lag associated with one or more filters in the transmitter is an integer multiple of π

,

(c) generating an update for one or more parameters of the compensator circuit, wherein said generating includes;

capturing a block of samples from the feedback path, computing real and imaginary parts of the complex Fourier transform corresponding to the frequency kf_b from the block of samples, wherein f_b is the frequency of the orthogonal pair of tones, wherein k is one or two, and computing the update for the one or more parameters using said real and imaginary parts of the complex Fourier transform corresponding to frequency kf_b;

(d) supplying the updated one or more parameters to the compensator circuit;

(e) repeating (c) and (d) a number of times until a termination condition is achieved.

2. The method of claim 1, wherein the one or more errors include an inphase DC offset error and a quadrature DC offset error of the transmitter, wherein k equals 1.

3. The method of claim 2 further comprising:

prior to (b), setting a quadrature DC offset parameter of the compensator circuit equal to zero and setting an inphase DC offset parameter of the compensator equal to a nonzero value.

4. The method of claim 2, wherein said adjusting the delay value includes:

(b1) capturing samples from the feedback path;

(b2) computing said real and imaginary parts of the complex Fourier transform corresponding to the frequency f_b from the captured samples;

(b3) adjusting the delay value of the delay unit; and

(b4) repeating (b1) through (b3) in order to maximize said real part of the complex Fourier transform corresponding to the frequency f_b.

5. The method of claim 1, wherein the one or more errors are include a phase imbalance error and a gain imbalance error, wherein k equals 2.

6. The method of claim 5 further comprising:

prior to (b), setting a phase imbalance parameter of the compensator equal to zero and setting a gain imbalance parameter of the compensator equal to a nonzero value.

7. The method of claim 5, wherein said adjusting the delay value includes:

(b1) capturing samples from the feedback path;

(b2) computing said real and imaginary parts of the complex Fourier transform corresponding to the frequency 2f_b from the captured samples;

(b3) adjusting the delay value of the delay unit; and

(b4) repeating (b1) through (b3) in order to maximize the real part of the complex Fourier transform.

8. The method of claim 1, wherein said termination condition is a condition that a count of completed repetitions of (c) and (d) is greater than or equal to a predetermined maximum value.

9. The method of claim 1, wherein said computing the update for the one or more parameters includes:

computing a first increment for a first of the one or more parameters based on said real part of the complex Fourier transform corresponding to the frequency kf_b, and adding the first increment to a previous value of the first parameter.

10. The method of claim 1, wherein said computing the update for the one or more parameters includes:

computing a second increment for a second of the one or more parameters based on said imaginary part of the complex Fourier transform corresponding to the frequency kf_b, and adding the second increment to a previous value of the second parameter.

12. The transmitter of claim 1, wherein the compensator circuit includes a 2×

2 matrix multiply circuit and a pair of scalar multiplication units, wherein the 2×

2 matrix multiply circuit is configured to perform a matrix multiplication operation on the first pair of discrete-time signals in order to generate an intermediate pair of discrete-time signals, wherein the pair of scalar multiplication units are configured to multiply the intermediate pair of discrete-time signals respectively by a pair of gain parameter values in order to obtain a pair of scaled discrete-time signals.

13. The transmitter of claim 12, wherein the one or more compensation parameters of the compensator circuit include a phase imbalance parameter, wherein the compensator circuit is configured to receive the phase imbalance parameter from the control unit and to determine coefficients of the matrix multiplication operation based on the phase imbalance parameter.

11. A transmitter comprising:

a compensator circuit configured to receive and operate on a first pair of discrete-time signals in order to generate a second pair of discrete-time signals;

a pair of digital-to-analog (D/A) conversion units configured to convert the second pair of discrete-time signals respectively into a third pair of analog signals;

a quadrature modulator configured to operate on the third pair of analog signals in order to generate an output RF signal;

a feedback circuit configured to detect an envelope signal from the output RF signal and to apply a time delay to the envelope signal in order to generate a feedback signal; and

a control unit configured to adjust an amount of the time delay and to compute and update one or more compensation parameters of the compensator circuit, wherein the compensator circuit is configured to operate on the first pair of discrete-time signals so that the second pair of discrete-time signals compensate for one or more errors in the transmitter.

14. The transmitter of claim 11, wherein the compensator circuit includes a pair of DC offset circuits in order to compensate for DC offset errors in the transmitter.

15. The transmitter of claim 11 further comprising an inverse Fast Fourier Transform (IFFT) unit configured to receive and operate on blocks of coefficients in order to generate the first pair of discrete-time signals.

16. The transmitter of claim 15, wherein the control unit is configured to control a selection of the blocks of coefficients from a memory.

17. The transmitter of claim 11, wherein feedback circuit includes:

a nonlinear device configured to operate on the output RF signal in order to generate a signal s(t); and

a bandpass filter configured to filter the signal s(t) in order produce the envelope signal.

18. The transmitter of claim 16, wherein the feedback circuit includes an adjustable delay unit configured to perform said application of the time delay to the envelope signal, wherein the adjustable delay unit is configured to receive a control signal, from the control unit, indicating said amount of the time delay.

19. The transmitter of claim 11, wherein the compensator circuit, the pair of D/A conversion units and the control units are fabricated on a first chip, wherein the quadrature modulator and the feedback circuit are fabricated on a second chip.

20. The transmitter of claim 11, wherein the transmitter is fabricated on a single chip.

21. The transmitter of claim 11, wherein the control unit is configured to read and execute program instructions stored in a memory.