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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT WITH FULLY DEPLETED AND PARTIALLY DEPLETED TRANSISTORS

  • US 20080064174A1
  • Filed: 08/29/2007
  • Published: 03/13/2008
  • Est. Priority Date: 08/31/2006
  • Status: Active Grant
First Claim
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1. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:

  • a) forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate;

    b) attaching the upper surface of the formed structure to a support wafer;

    c) eliminating said substrate until the silicon-germanium layer is apparent;

    d) depositing a mask and opening this mask at the locations of transistors which are desired to be fully depleted;

    e) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon and the silicon-germanium moves in the silicon layer; and

    f) eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

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