METHOD FOR FORMING SEMICONDUCTOR DEVICE

• US 20080064192A1
• Filed: 08/29/2007
• Published: 03/13/2008
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Kim, Jea-Hee
• Granted Patent: US 7,588,978 B2
• Time in Patent Office: Days
• US Class Current: 438/532
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness corresponding to a high-voltage (HV) area of the well. A first photoresist pattern may be formed over a surface of the first oxide layer. An etching process may be performed using the first photoresist pattern as a mask, so that the first oxide layer is selectively etched until the semiconductor substrate is partially exposed, to form a first oxide layer pattern. A second oxide layer may be deposited over a surface of the semiconductor substrate including the first oxide layer pattern using the first photoresist pattern as a mask, the second oxide layer having a predetermined thickness corresponding to a low-voltage (LV) area of the well. The first photoresist pattern may be removed. A polysilicon layer may be coated over the surface of the semiconductor substrate including the first oxide layer pattern and the second oxide layer. A second photoresist pattern may be formed over a surface of the polysilicon layer. An etching process may be performed using the second photoresist pattern as a mask, so that the polysilicon layer is selectively etched until the first oxide layer pattern and the second oxide layer are partially exposed. The second photoresist pattern may be removed. An impurity ion-implantation process may be performed using the polysilicon layer, the first oxide layer pattern and the second oxide layer as a hard mask, to form a drift area in the semiconductor substrate.

Claims

1. A method comprising:

depositing a first oxide layer over a surface of a semiconductor substrate including high voltage and low voltage wells, the first oxide layer having a predetermined thickness corresponding to a high voltage area of the well;

forming a first photoresist pattern over a surface of the first oxide layer, performing an etching process using the first photoresist pattern as a mask, so that the first oxide layer is selectively etched until the semiconductor substrate is partially exposed, to form a first oxide layer pattern;

depositing a second oxide layer over a surface of the semiconductor substrate including the first oxide layer pattern using a first photoresist pattern as a mask, the second oxide layer having a predetermined thickness corresponding to a low voltage area of the well;

removing said first photoresist pattern, and coating a polysilicon layer over the surface of the semiconductor substrate including the first oxide layer pattern and the second oxide layer;

forming a second photoresist pattern over a surface of the polysilicon layer, performing an etching process using the second photoresist pattern as a mask, so that the polysilicon layer is selectively etched until the first oxide layer pattern and the second oxide layer are partially exposed; and

removing the second photoresist pattern, performing an impurity ion implantation process using the polysilicon layer, the first oxide layer pattern, and the second oxide layer as a hard mask, to form a drift area in the semiconductor substrate.

2. The method of claim 1, wherein the thickness corresponding to a high voltage is about 100 Å

to 200 Å

.

3. The method of claim 1, wherein the thickness corresponding to a low voltage is about 300 Å

to 400 Å

.

4. The method of claim 1, wherein in the impurity ion implantation process N-impurity ions or P-impurity ions are implanted.

5. The method of claim 1, wherein the drift area is formed of an N-drift area or P-drift area by the impurity ion implantation.

6. A apparatus configured to:

deposit a first oxide layer over a surface of a semiconductor substrate including high voltage and low voltage wells, the first oxide layer having a predetermined thickness corresponding to a high voltage area of the well;

form a first photoresist pattern over a surface of the first oxide layer, perform an etching process using the first photoresist pattern as a mask, so that the first oxide layer is selectively etched until the semiconductor substrate is partially exposed, to form a first oxide layer pattern;

deposit a second oxide layer over a surface of the semiconductor substrate including the first oxide layer pattern using a first photoresist pattern as a mask, the second oxide layer having a predetermined thickness corresponding to a low voltage area of the well;

remove said first photoresist pattern, and coat a polysilicon layer over the surface of the semiconductor substrate including the first oxide layer pattern and the second oxide layer;

form a second photoresist pattern over a surface of the polysilicon layer, perform an etching process using the second photoresist pattern as a mask, so that the polysilicon layer is selectively etched until the first oxide layer pattern and the second oxide layer are partially exposed; and

remove the second photoresist pattern, perform an impurity ion implantation process using the polysilicon layer, the first oxide layer pattern, and the second oxide layer as a hard mask, to form a drift area in the semiconductor substrate.

7. The apparatus of claim 6, wherein the thickness corresponding to a high voltage is about 100 Å

to 200 Å

.

8. The apparatus of claim 6, wherein the thickness corresponding to a low voltage is about 300 Å

to 400 Å

.

9. The apparatus of claim 6, wherein in the impurity ion implantation process N-impurity ions or P-impurity ions are implanted.

10. The apparatus of claim 6, wherein the drift area is formed of an N-drift area or P-drift area by the impurity ion implantation.