High bandwidth memory interface
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0 Petitions
Accused Products
Abstract
This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.
109 Citations
32 Claims
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1. (canceled)
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2. In a selected one of a semiconductor memory device and memory controller device, a method of receiving data comprising:
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a) resistively terminating data bus terminals and an at least one data clock terminal of the selected one of the two devices;
b) receiving an at least one data clock signal on said data clock terminal;
c) generating a data sampling clock with said received data clock signal;
d) receiving data signals on said data bus terminals; and
e) sampling the received data signals with said generated data sampling clock. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A semiconductor device for use in a memory system and configured for communication over a bus, the semiconductor device comprising:
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a) a plurality of microelectronic terminals for coupling to the bus, said microelectronic terminals including data terminals and at least one data clock terminal;
b) output drivers for driving data signals and at least one data clock signal on said data terminals and said at least one data clock terminal, respectively; and
c) termination devices coupled to said data terminals and said at least one data clock terminal. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of carrying out data operations in a Dynamic Random Access Memory (DRAM) system that includes a DRAM controller and at least one DRAM, the DRAM controller and the DRAM in communication with each other over a data bus, the method comprising:
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a) within at least a selected one of the DRAM and the DRAM controller;
i) resistively terminating data bus terminals and an at least one data clock terminal, said data bus terminals connected to the data bus;
ii) receiving an at least one data clock signal on said data clock terminal;
iii) generating a data sampling clock with said data clock signal;
iv) receiving data signals on said data bus terminals; and
v) sampling said data signals with said data sampling clock.
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Specification
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- Resources
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current711/105
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CPC Class CodesG06F 1/12 Synchronisation of differen...G06F 13/1689 Synchronisation and timing ...G06F 13/4234 being a memory busG06F 13/4243 with synchronous protocolG11C 5/06 Arrangements for interconne...G11C 8/18 Address timing or clocking ...Y02D 10/00 Energy efficient computing,...
