Direct cache access in multiple core processors

• US 20080065832A1
• Filed: 09/08/2006
• Published: 03/13/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gilbert, Jeffrey D., Srivastava, Durgesh
• Granted Patent: US 7,555,597 B2
• Time in Patent Office: Days
• US Class Current: 711/130
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0879 Burst mode

Abstract

Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

Claims

1. A processor comprising:

a first logic to cause storage of data corresponding to one or more direct cache access requests in a storage unit; and

a second logic to generate a read request corresponding to one of the direct access requests.

2. The processor of claim 1, further comprising a third logic to determine whether one or more incoming memory requests correspond to the one or more direct cache access requests.

3. The processor of claim 2, wherein the incoming memory requests that correspond to the direct cache access requests comprise a direct cache access hint.

4. The processor of claim 1, wherein the direct cache access requests correspond to snoop requests.

5. The processor of claim 1, wherein each entry of the storage unit comprises one or more of an address field, a validity field, or a wait field.

6. The processor of claim 5, wherein the second logic generates the read request after a predetermined time period and wherein the predetermined time period corresponds to a value stored in the corresponding wait field of an entry of the storage unit.

7. The processor of claim 1, further comprising a third logic to transmit the read request to a system memory.

8. The processor of claim 1, further comprising a shared cache to store data transmitted in response to the read request.

9. The processor of claim 8, wherein the shared cache comprises one or more of a mid-level cache, a last level cache, or combinations thereof.

10. The processor of claim 1, further comprising a core portion and an uncore portion.

11. The processor of claim 10, wherein the uncore portion comprises the first and second logics.

12. The processor of claim 10, wherein the core portion comprises a plurality of processor cores.

13. The processor of claim 1, wherein one or more of the first logic, the second logic, a plurality of processor cores, or a shared cache are on a same integrated circuit die.

14. A method comprising:

storing data corresponding to a memory request in a direct cache access queue after determining that the memory request comprises a direct cache access hint; and

generating a read request corresponding to the memory request after a predetermined time period.

15. The method of claim 14, further comprising accessing a wait field of an entry of the direct cache access queue that corresponds to the memory request to determine the predetermined time period.

16. The method of claim 14, further comprising decoding a snoop request to determine whether the snoop request corresponds to the memory request.

17. The method of claim 14, wherein storing the data comprises storing one or more of an address field, a validity field, or a wait field corresponding to the memory request in the direct cache access queue.

18. The method of claim 14, further comprising transmitting the read request to a system memory.

19. The method of claim 14, further comprising storing data transmitted in response to the read request in a shared cache.

20. The method of claim 14, further comprising:

updating a write pointer of the direct cache access queue after storing the data in the direct cache access queue; and

updating a read pointer of the direct cache access queue after generating the read request.

21. A computing system comprising:

an input/output (I/O) device to cause transmission of a snoop request; and

at least one processor comprising;

a direct cache access queue to store a plurality of bits representing a direct cache access request corresponding to the snoop request; and

a hint check logic to decode the snoop request and cause storage of the plurality of bits in the direct cache access queue in response to a direct cache access hint embedded with the snoop request.

22. The system of claim 21, further comprising a read request generation logic to generate a read request corresponding to the direct cache access request.

23. The system of claim 21, further comprising a shared cache to store data returned in response to the read request.

24. The system of claim 21, wherein the at least one processor comprises a plurality of processor cores.

25. The system of claim 21, wherein the I/O device comprises one or more of a network interface device, a disk drive, or an audio device.

26. An apparatus comprising:

a first logic to detect whether a memory access request corresponds to a direct cache access request and to cause data corresponding to the direct cache access request to be stored in a storage unit; and

a second logic to generate a read request corresponding to the direct access requests, the second logic to generate the read request in response to an expiration of a time period corresponding to the direct cache access request.

27. The apparatus of claim 26, wherein the direct cache access request corresponds to a snoop request.

28. The apparatus of claim 26, further comprising a shared cache to store data transmitted in response to the read request.

29. The apparatus of claim 26, wherein the memory access request that corresponds to the direct cache access request comprises a direct cache access hint.

30. The apparatus of claim 26, wherein one or more of the first logic, the second logic, a plurality of processor cores, or a shared cache are on a same integrated circuit die.