DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20080067519A1
• Filed: 09/14/2007
• Published: 03/20/2008
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Epson Imaging Devices Corporation (Seiko Group)
• Inventors: Sakurai, Toru, Morimoto, Yusaku, Umetani, Yutaka
• Granted Patent: US 8,071,985 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1281 by using structural features to control crystal growth, e.g. placement of grain filters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

The invention provides a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate, where dielectric strength between electrodes forming the storage capacitor is enhanced for increasing the yield. In the storage capacitor, a lower storage capacitor electrode, a thin lower storage capacitor film, a polysilicon layer, an upper storage capacitor film and an upper storage capacitor electrode are layered. The polysilicon layer is formed by crystallization by laser annealing. The polysilicon layer of the storage capacitor is microcrystalline and thus the flatness of its surface is enhanced. The pattern of the polysilicon layer (storage capacitor electrode) is formed larger than the bottom portion of an opening, and the edge of its peripheral portion is located on a buffer film on the slant portion of the opening or on the buffer film on the outside of the opening.

Claims

1. A display device comprising:

a substrate;

a thin film transistor disposed on the substrate and configured to receive a display signal,

the thin film transistor comprising;

a light-shielding layer disposed on the substrate,

a buffer film disposed on the light shielding layer,

a polysilicon layer disposed on the buffer film,

a gate insulation film disposed on the polysilicon layer, and

a gate electrode disposed on the gate insulation film; and

a storage capacitor disposed on the substrate and configured to store the display signal supplied by the thin film transistor,

the storage capacitor comprising;

a lower storage capacitor electrode disposed on the substrate,

a lower storage capacitor film disposed on the buffer film and being in contact with the lower storage capacitor electrode through an opening in the buffer film, the lower storage capacitor film being thinner than the buffer film,

a middle storage capacitor electrode disposed on the lower storage capacitor film and formed of the polysilicon layer, a grain size of the polysilicon layer of the middle storage capacitor electrode being smaller than a grain size of the polysilicon layer of the thin film transistor,

an upper storage capacitor film disposed on the middle storage capacitor electrode, and

an upper storage capacitor electrode disposed on the upper storage capacitor film.

2. The display device of claim 1, wherein the opening in the buffer film has a slant portion so that a bottom of the opening is smaller than a top of the opening, the middle storage capacitor electrode is larger than the bottom of the opening so that an edge portion of the middle storage capacitor electrode is located on the slant portion, and the grain size of the polysilicon layer of the middle storage capacitor electrode is smaller than a grain size of the polysilicon layer located on the slant portion.

3. The display device of claim 1, wherein the middle storage capacitor electrode is larger than a bottom of the opening so that an edge portion of the middle storage capacitor electrode is located on the buffer film, and the grain size of the polysilicon layer of the middle storage capacitor electrode is smaller than a grain size of the polysilicon layer along the edge portion of the middle storage capacitor electrode.

4. The display device of claim 1, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

5. The display device of claim 2, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

6. The display device of claim 3, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

7. The display device of claim 1, wherein a thickness of the lower storage capacitor film is 100 nm or less.

8. The display device of claim 2, wherein a thickness of the lower storage capacitor film is 100 nm or less.

9. The display device of claim 3, wherein a thickness of the lower storage capacitor film is 100 nm or less.

10. The display device of claim 2, wherein the edge portion of the middle storage capacitor electrode does not overlap the upper storage capacitor electrode.

11. The display device of claim 3, wherein the edge portion of the middle storage capacitor electrode does not overlap the upper storage capacitor electrode.

12. A method of manufacturing a display device, comprising:

forming a light-shielding layer and a lower storage capacitor electrode on a substrate;

forming a buffer film on the light-shielding layer and the lower storage capacitor electrode;

forming an opening in the buffer film to expose at least partially the lower storage capacitor electrode;

forming a lower storage capacitor film thinner than the buffer film on the exposed lower storage capacitor electrode;

forming, after the formation of the lower storage capacitor film, an amorphous silicon layer on the buffer film and the lower storage capacitor electrode;

transforming the amorphous silicon layer into a polysilicon layer by annealing;

forming a middle storage capacitor electrode by patterning the polysilicon layer;

forming a gate insulation film on the polysilicon layer and an upper storage capacitor film on the middle storage capacitor electrode; and

forming a gate electrode on the gate insulation film and an upper storage capacitor electrode on the upper storage capacitor film.

13. The method of claim 12, wherein the middle storage capacitor electrode is formed so as to be larger than a bottom portion of the opening and have an edge located on the buffer film on a slant portion of the opening.

14. The method of claim 12, wherein the storage capacitor electrode is formed so as to be larger than a bottom portion of the opening and have an edge located on the buffer film on an outside of the bottom portion.

15. The method of claim 12, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

16. The method of claim 13, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

17. The method of claim 14, wherein a sum of thicknesses of the buffer film and the lower storage capacitor film is 300 nm or more.

18. The method of claim 12, wherein a thickness of the lower storage capacitor film is 100 nm or less.

19. The method of claim 13, wherein a thickness of the lower storage capacitor film is 100 nm or less.

20. The method of claim 14, wherein a thickness of the lower storage capacitor film is 100 nm or less.