Stacked memory and method for forming the same

• US 20080067573A1
• Filed: 02/22/2007
• Published: 03/20/2008
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Young-Chul, Cho, Won-Seok, Jung, Soon-Moon, Kim, Jong-Hyuk, Jang, Jae-Hoon, Cho, Hoo-Sung
• Granted Patent: US 7,683,404 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

Claims

1. A stacked memory comprising:

at least two semiconductor layers, each of the at least two semiconductor layers including a memory cell array; and

a transistor in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers

2. The stacked memory of claim 1, wherein the transistor is configured to drive the memory cell array of each of the at least two semiconductor layers.

3. The stacked memory of claim 1, wherein the transistor comprises a low-voltage transistor.

4. The stacked memory of claim 1, wherein the transistor is configured to read data from a memory cell of the memory cell array of the at least two semiconductor layers.

5. The stacked memory of claim 1, wherein the transistor comprises a low-voltage, and wherein the stacked memory further comprises a high-voltage transistor in a peripheral circuit region of a lowermost semiconductor layer or a semiconductor layer interposed between the uppermost and lowermost semiconductor layers.

6. The stacked memory of claim 5, wherein the high-voltage transistor is configured to program and/or erase a memory cell of the memory cell array of the at least two semiconductor layers.

7. The stacked memory of claim 1, wherein the memory cell array of each of the at least two semiconductor layers comprises:

a memory cell string of memory cells connected in series;

a string selection transistor connected to a first end memory cell of the memory cell string; and

a ground selection transistor connected to a second end memory cell of the memory cell string.

8. The stacked memory of claim 7, further comprising:

a bit line on the uppermost semiconductor layer and connected to the string selection transistors of the at least two semiconductor layers;

common source regions alongside the ground selection transistors of the at least two semiconductor layers, respectively; and

a source contact electrically connecting the common source regions.

9. The stacked memory of claim 7, wherein the transistor comprises a low-voltage transistor, and wherein the stacked memory further comprises a high-voltage transistor in a peripheral circuit region of a lowermost semiconductor layer of the at least semiconductor layers or a semiconductor layer interposed between the uppermost and lowermost semiconductor layers.

10. The stacked memory of claim 9, further comprising:

a bit line formed on the uppermost semiconductor layer and connected to the string selection transistors of the at least two semiconductor layers;

common source regions alongside the ground selection transistors of the at least two semiconductor layers, respectively; and

a source contact electrically connecting the common source regions.

11. A method of forming a stacked memory, comprising:

forming a first memory cell array at a first semiconductor layer;

forming a second semiconductor layer on the first semiconductor layer having the first memory cell array;

forming a second memory cell array in a cell array region of the second semiconductor layer; and

forming a first transistor in a peripheral circuit region of the second semiconductor layer.

12. The method of claim 11, wherein forming a second memory cell array comprises forming a first impurity diffusion region, and forming a first transistor comprises forming a second impurity diffusion region, and wherein the second impurity diffusion region is formed after the first impurity diffusion region.

13. The method of claim 12, wherein the first transistor is configured to drive the first and second memory cell arrays.

14. The method of claim 12, wherein the first transistor is configured to read a data from a memory cell of first and second memory cell arrays.

15. The method of claim 11, wherein the first transistor is configured to drive the first and second memory cell arrays.

16. The method of claim 11, further comprising forming a second transistor in a peripheral circuit region of the first semiconductor layer or in a peripheral circuit region of the second semiconductor layer, the second transistor configured to operate at a higher voltage than the first transistor.

17. The method of claim 11, wherein the forming of the first memory cell array and the forming of the second memory cell array comprise:

forming a memory cell string of memory cells connected in series; and

forming a string selection transistor and a ground selection transistor, the string selection transistor connected to a first end memory cell of the memory cell string, and the ground selection transistor connected to a second end memory cell of the memory cell string.

18. The method of claim 17, further comprising forming a source contact electrically connected to ground selection transistors of the first and second semiconductor layers.

19. The method of claim 17, further comprising forming a bit line electrically connected to the string selection transistors of the first and second semiconductor layers.

20. The method of claim 19, further comprising forming a local interconnection electrically connected to the first transistor when the bit line is formed.