Inverted-trench grounded-source FET structure with trenched source body short electrode

• US 20080067584A1
• Filed: 09/17/2006
• Published: 03/20/2008
• Est. Priority Date: 09/17/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Hebert, Francois, Lui, Sik K
• Granted Patent: US 8,008,716 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Claims

1. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprising:

a vertical current conducting channel between said source and said drain disposed along a trenched gate padded by a gate oxide disposed on sidewalls of a trench opened in said semiconductor substrate; and

a source-body short structure constituting a conductive plug extending downwardly disposed in a buried conductor trench for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate.

2. The iT-FET semiconductor device of claim 1 wherein:

said vertical current conducting channel further comprising a doped channel region disposed in said substrate and surrounding a bottom portion of said trench extending to said source disposed at said bottom of said substrate.

3. The iT-FET semiconductor device of claim 2 further comprising:

a drift region disposed near said top surface of said substrate surrounding an upper portion of said trench and encompassing said drain; and

a link region disposed below said drift region and extending downwardly to said doped channel region for linking said drift region and said doped channel region.

4. The iT-FET semiconductor device of claim 2 wherein:

said conductive plug of said body-source short structure further comprising a conductive silicide of Titanium plug extending downwardly from a bottom portion of said trench to said source region.

5. The iT-FET semiconductor device of claim 2 wherein:

said conductive plug of said body-source short structure further comprising a conductive silicide of Cobalt plug extending downwardly from a bottom portion of said trench to said source region.

6. The iT-FET semiconductor device of claim 2 wherein:

said conductive plug of said body-source short structure further comprising a conductive silicide of Tungsten plug extending downwardly from a bottom portion of said trench to said source region.

7. The iT-FET semiconductor device of claim 1 further comprising:

a source-doped region disposed below a bottom surface of said trenched gate surrounded by said doped channel region.

8. The iT-FET semiconductor device of claim 1 wherein:

said trench gate further comprising a thick spacer-oxide layer disposed on an upper portion of said sidewalls for insulating said trenched gate from said drain disposed near a top surface of said substrate to further reduce a gate-drain coupling capacitance.

9. The iT-FET semiconductor device of claim 1 wherein:

said source further comprising a N+ doped region disposed on said bottom of said substrate.

10. The iT-FET semiconductor device of claim 9 wherein:

said drain further comprising a N+ doped region disposed on said top of said substrate.

11. The iT-FET semiconductor device of claim 9 wherein:

said doped channel region comprising a P doped region disposed in said substrate and surrounding a bottom portion of said trench extending to said source.

12. The iT-FET semiconductor device of claim 9 wherein:

said bottom of said substrate further comprising a N+ doped contact-enhancement zone for enhancing an electrical contact between said source-body short to said source region.

13. The iT-FET semiconductor device of claim 1 further comprising:

a termination area comprising a trenched gate runner electrically connecting to said treched gate for electrically connecting to a gate metal disposed in said termination area.

14. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

15. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

16. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising an enhancement mode metal oxide semiconductor field effect transistor (MOSFET) device.

17. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a depletion mode metal oxide semiconductor field effect transistor (MOSFET) device.

18. The iT-FET semiconductor device of claim 1 wherein:

Said iT-FET further comprising a source-body short structure constituting a conductive plug extending downwardly disposed in a conductor trench open from said top of semiconductor substrate for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate, said source-body short plug electrically connects to a source electrode displace on top of said top of semiconductor substrate.

19. The iT-FET semiconductor device of claim 1 wherein:

said source-body short structure constituting said conductive plug disposed in said buried conductor trench disposed in an active cell area on said semiconductor substrate for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate.

20. The iT-FET semiconductor device of claim 1 further comprising:

a plurality of said source-body short structure formed as buried conductive plug disposed in a plurality of buried conductor trenches distributed through said iT-FET semiconductor device.

21. The iT-FET semiconductor device of claim 3 wherein comprising:

said drift region is a N-drift region and is left unconnected for constituting a floating N-drift region and having substantially a source voltage whereby a die-sawing damage to said iT-FET device caused by grounding said N-drift region is reduced.

22. The iT-FET semiconductor device of claim 3 wherein comprising:

said body region is formed in an N-epitaxial layer in said semiconductor substrate as an implanted body region.

23. The iT-FET semiconductor device of claim 3 wherein comprising:

said source-body short structure constituting a conductive plug extending downwardly from a bottom surface of a buried conductor trench disposed in a termination area for on said semiconductor substrate for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate and further for shorting said source disposed on said bottom of said substrate to a source pad disposed on a top surface of said semiconductor substrate.

24. An integrated circuit device comprising:

an inverted power MOS field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate to function as a highside FET for a buck converter; and

a power MOSFET device with a drain disposed on said semiconductor substrate for integrating with said iT-FET to function as a low-side FET for a buck converter.

25. The integrated circuit device of claim 24 wherein:

said low-side FET further comprising an integrated Schottky diode.

26. The integrated circuit device of claim 25 wherein:

said Schottky diode is a trenched Schottky diode.

27. The integrated circuit device of claim 24 wherein:

said FET device includes a trenched gate surrounded by source regions near said top surface of said semiconductor substrate encompassed in a body region of said FET.

28. The integrated circuit device of claim 24 wherein:

said iT-FET functioning as said high-side FET semiconductor device and said FET device functioning as a low-side FET are integrated on a single die of said semiconductor substrate with said source of said iT-FET semiconductor device is in direct electric connection to said drain of said FET device at said bottom of said semiconductor substrate whereby said buck converter is manufactured as a single chip on said single die.

29. A method of manufacturing an integrated circuit device for buck converter application comprising:

simultaneously manufacturing an inverted field-effect-transistor (iT-FET) semiconductor device to function as a high-side FET with a FET device to function as a low-side FET on a same semiconductor substrate by forming a source of said iTFET semiconductor FET on a bottom surface of said substrate for direct electric connection to a drain of said FET.

30. The method of claim 29 wherein:

said step of simultaneously manufacturing said inverted field-effect-transistor (iT-FET) semiconductor device and said FET further comprising a step of integrating said iT-FET semiconductor device and said FET on a single die of said semiconductor substrate whereby said buck converter is manufactured as a single chip on said single die without a leadframe.

31. The method of claim 29 wherein:

said step of simultaneously manufacturing said inverted field-effect-transistor (iT-FET) semiconductor device and said FET further comprising a step of integrating a Schottky diode.