High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same

• US 20080067586A1
• Filed: 11/05/2007
• Published: 03/20/2008
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard, Chan, Wai, Ryu, HyungSik, Chen, Jun-Wei, Disney, Donald
• Granted Patent: US 7,812,393 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66106 : Zener diodes
• CPC Class Codes: H01L 29/66659 : with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/866 : Zener diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Claims

1-24. -24. (canceled)

25. An extended drain MOSFET formed in a semiconductor substrate, the substrate not comprising an epitaxial layer, the MOSFET comprising:

a field oxide layer formed at a surface of the substrate, an opening being forming in the field oxide layer, the opening being bounded by edges of the field oxide layer;

a conformal well of a first conductivity type formed in the substrate, the well comprising a deep portion under the opening in the field oxide layer and a shallow portion under a portion of the field oxide layer, the deep portion extending deeper into the substrate than the shallow portion, the well comprising at least two dopant regions implanted at different energies;

a drain region of a second conductivity type formed in the well and located adjacent the surface of the substrate;

a drift region of the second conductivity type formed in the well and located adjacent the surface of the substrate and the drain region, a doping concentration of the drift region being lower than a doping concentration of the drain region, the drift region having a substantially planar lower boundary;

a source region of the second conductivity type located adjacent the surface of the substrate, the source region being separated from the drift region by a channel region;

a gate dielectric layer over the channel region; and

a gate over the gate dielectric layer.

26. The extended drain MOSFET of claim 25 wherein within the conformal well a deeper dopant region has a doping concentration that is greater than a doping concentration of at least one dopant region located above the deeper dopant region.

27. The extended drain MOSFET of claim 25 wherein the drain region is laterally surrounded by the channel region.

28. The extended drain MOSFET of claim 25 further comprising a region of the second conductivity type located below the drain region, the region of second conductivity type extending deeper into the substrate than the drift region.

29. The extended drain MOSFET of claim 25 wherein the substrate is of the second conductivity type.

30. The extended drain MOSFET of claim 25 wherein the substrate is of the first conductivity type.

31. An extended drain MOSFET formed in a semiconductor substrate, the substrate not comprising an epitaxial layer, the MOSFET comprising:

a field oxide layer formed at a surface of the substrate, an opening being formed in the field oxide layer;

a conformal well formed in the substrate, the well comprising a shallow portion under the field oxide region and a deep portion under the opening in the field oxide layer, the deep portion extending deeper into the substrate than the shallow portion;

a body region of a first conductivity type adjacent the surface of the substrate in the well;

a source region of a second conductivity type adjacent the surface of the substrate and adjacent the body region;

a drain region of the second conductivity type adjacent the surface of the substrate in the well;

a gate and a gate dielectric layer overlying the surface of the substrate in the well, the gate overlying a channel region;

a first drain extension of the second conductivity type extending laterally from the drain to the channel region; and

a second drain extension of the second conductivity type extending laterally from the drain to an edge of the opening in the field oxide layer;

wherein a length of the first drain extension is different from a length of the second drain extension.

32. The extended drain MOSFET of claim 31 further comprising a source extension of the second conductivity type extending laterally from the source region to the channel region.

33. The extended drain MOSFET of claim 31 wherein the substrate is of the second conductivity type and the well is of the first conductivity type.

34. The extended drain MOSFET of claim 33 wherein the well comprises a vertical series of dopant regions implanted at different energies.

35. The extended drain MOSFET of claim 34 further comprising a heavily-doped region of the first conductivity type within the well below the drain region, the heavily-doped region having a doping concentration greater than the doping concentration of the portions of the well surrounding the heavily-doped region.

36. The extended drain MOSFET of claim 31 wherein the substrate and the well are of the first conductivity type.

37. The extended drain MOSFET of claim 36 wherein the well comprises a vertical series of dopant regions implanted at different energies.

38. The extended drain MOSFET of claim 37 further comprising a heavily-doped region of the second conductivity type within the well below the drain region, the heavily-doped region having a doping concentration greater than the doping concentration of the portions of the well surrounding the heavily-doped region.

39-91. -91. (canceled)