Insulated-gate field-effect thin film transistors

• US 20080067594A1
• Filed: 11/19/2007
• Published: 03/20/2008
• Est. Priority Date: 07/08/2002
• Status: Abandoned Application

• Current Assignee: Liberty Patents LLC
• Original Assignee: Liberty Patents LLC
• Inventors: Madurawe, Raminda
• Application Number:
  US11/985,829
• Publication Number:
  US 20080067594A1
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor thin film Gated-FET device, comprising: a resistive thin film channel region positioned between a source and a drain region, said channel region comprising a lower level of said source and drain majority carrier type; and a gate region coupled to the channel region by a dielectric region, wherein a first gate voltage modulates the channel resistance to a substantially non-conductive state by fully depleting majority carriers from the thin film channel region. Said device, wherein a second gate voltage modulates the channel resistance to a substantially conductive state by leaving adequate majority carriers in the thin film layer channel region.

Claims

1. A semiconductor thin film Gated-FET device, comprising:

a semiconductor thin film channel region positioned between source and drain regions, the channel region comprised of source and drain region majority carrier type; and

a gate region positioned adjacent to the thin film channel region, the gate region coupled to the channel region by a dielectric region, the gate region comprised of;

a first gate voltage to fully deplete majority carriers in the channel region to decouple source and drain regions; and

a second gate voltage to allow adequate majority carriers in the channel region to couple source and drain regions.

2. The device of claim 1, wherein the source and drain regions are formed in substantially heavily doped regions of the semiconductor thin film layer, and wherein:

a source terminal is coupled to the source region, a drain terminal is coupled to the drain region, and the drain to source current flow is modulated by the gate voltage.

3. The device of claim 1, wherein the channel region comprises one of:

a single crystal, a polycrystalline, a re-crystallized and any other semiconductor material.

4. The device of claim 1, wherein the gate region comprises one of a conductor, a refractory metal, a heavily doped poly-Silicon and a doped semiconductor material.

5. The device of claim 1, wherein the dielectric region comprises one of an oxide, an oxy-nitride, a nitride and any other insulating material.

6. The device of claim 1, further comprising a third gate voltage that depletes the majority carriers in channel region by exactly the thin-film thickness, wherein the thin film channel is at onset of coupling between source and drain regions.

7. The device of claim 6, further comprising an off state when the gate voltage is between the first and third voltage levels, wherein the source is decoupled from drain.

8. The device of claim 6, further comprising an on state when the gate voltage is between the third and second voltage levels, wherein the source is coupled to drain.

9. The device of claim 1, wherein the source, drain and channel regions comprise N type majority carriers.

10. The device of claim 1, wherein the source, drain and channel regions comprise P type majority carriers.

11. The device of claim 1 further comprising a fourth gate voltage that provides no depletion and no accumulation of majority carriers in channel region, wherein the channel majority carrier density is set by the net doping level of the thin film channel region.

12. A three terminal semiconductor thin film Gated-FET device, comprising:

a source region, a drain region and a gate region, each said region coupled to a terminal; and

a semiconductor thin film channel coupling the source to the drain, said channel having a lower level of said source and drain doping type; and

a dielectric layer coupling the gate to the channel, wherein;

a first voltage at the gate terminal fully depletes majority carriers in said thin film channel to decouple said source and drain regions; and

a second voltage at the gate terminal maintains adequate majority carriers in said thin film channel to couple said source and drain regions.

13. The device of claim 12, wherein the source and drain regions are formed in substantially heavily doped regions of the semiconductor thin film layer.

14. The device of claim 12, wherein the gate region comprises one of a conductor, a refractory metal, a heavily doped poly-Silicon and a doped semiconductor material.

15. The device of claim 12, wherein the dielectric region comprises one of an oxide, an oxy-nitride, a nitride and any other insulating material.

16. The device of claim 12, wherein the source, drain and channel regions are doped with one of N-type doping or P-type doping.

17. A semiconductor thin film Gated-FET device, comprising:

a resistive thin film channel region positioned between a source and a drain region, said channel region comprising a lower level of said source and drain majority carrier type; and

a gate region coupled to the channel region by a dielectric region, wherein a first gate voltage modulates the channel resistance to a substantially non-conductive state by fully depleting majority carriers from the thin film channel region.

18. The device of claim 17, wherein a second gate voltage modulates the channel resistance to a substantially conductive state by leaving adequate majority carriers in the thin film layer channel region.

19. The device of claim 17, wherein said non-conductive channel resistance is in a range of approximately 10 KOhm to 1 TOhm, and preferably in the range of 100 KOhm to 1 TOhm, and more preferably in the range of 1 MOhm to 1 TOhms.

20. The device of claim 18, wherein the ratio of the conductive channel resistance to non-conductive channel resistance is approximately greater than 100, and preferably greater than 1000, and more preferably greater than 10,000.