Structure and manufacturing method of a chip scale package

• US 20080067677A1
• Filed: 10/31/2007
• Published: 03/20/2008
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lin, Mou-Shiung, Lin, Chuen-Jye
• Granted Patent: US 7,902,679 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Claims

1. A chip package comprising:

a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;

a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer;

a copper pillar between said first pad and said first surface, wherein said copper pillar has a height between 10 and 100 micrometers;

a barrier metal layer between said first pad and said copper pillar, wherein said barrier metal layer is on said first pad, over said passivation layer and in said opening;

a nickel layer between said copper pillar and said first surface, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

a solder metal between said nickel layer and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;

an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and

a contact ball on said second surface.

2. The chip package of claim 1, wherein said passivation layer comprises silicon nitride.

3. The chip package of claim 1, wherein said passivation layer comprises polymer.

4. The chip package of claim 1, wherein said barrier layer comprises titanium.

5. The chip package of claim 1, wherein said ball grid array (BGA) substrate comprises a solder mask and a second pad separate from said solder mask, wherein said second pad is at a same horizontal level as said solder mask, and wherein said second pad has a circular shape.

6. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer;

a copper pillar between said first pad and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers;

a barrier metal layer between said first pad and said copper pillar, wherein said barrier metal layer is on said first pad, over said passivation layer and in said opening;

a nickel layer between said copper pillar and said substrate, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

a solder metal between said nickel layer and said substrate, wherein said solder metal is joined with said substrate; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.

7. The chip package of claim 6, wherein said passivation layer comprises silicon nitride.

8. The chip package of claim 6, wherein said passivation layer comprises polymer.

9. The chip package of claim 6, wherein said barrier layer comprises titanium.

10. The chip package of claim 6, wherein said substrate comprises a solder mask and a second pad separate from said solder mask, wherein said second pad is at a same horizontal level as said solder mask, and wherein said second pad has a circular shape.

11. A chip package comprising:

a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;

a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer;

a copper pillar between said semiconductor device and said first surface, wherein said copper pillar is connected to said first pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers;

a nickel layer between said copper pillar and said first surface, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

a solder metal between said nickel layer and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;

an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and

a contact ball on said second surface.

12. The chip package of claim 11, wherein said passivation layer comprises silicon nitride.

13. The chip package of claim 11, wherein said passivation layer comprises polymer.

14. The chip package of claim 11, wherein said nickel layer has a thickness between 1 and 10 micrometers.

15. The chip package of claim 11, wherein said ball grid array (BGA) substrate comprises a solder mask and a second pad separate from said solder mask, wherein said second pad is at a same horizontal level as said solder mask, and wherein said second pad has a circular shape.

16. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer;

a copper pillar between said semiconductor device and said substrate, wherein said copper pillar is connected to said first pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers;

a nickel layer between said copper pillar and said substrate, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

a solder metal between said nickel layer and said substrate, wherein said solder metal is joined with said substrate; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.

17. The chip package of claim 16, wherein said passivation layer comprises silicon nitride.

18. The chip package of claim 16, wherein said passivation layer comprises polymer.

19. The chip package of claim 16, wherein said nickel layer has a thickness between 1 and 10 micrometers.

20. The chip package of claim 16, wherein said substrate comprises a solder mask and a second pad separate from said solder mask, wherein said second pad is at a same horizontal level as said solder mask, and wherein said second pad has a circular shape.