Random Seed Stability with Fuses
First Claim
1. A circuit for stabilizing soft bits in a bit stream, the circuit comprising:
- a first register adapted to receive an initial read of the bit stream,a second register adapted to receive a subsequent read of the bit stream,a comparator adapted to compare the initial read of the bit stream to the subsequent read of the bit stream,a third register adapted to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, andan accumulator adapted to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
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Accused Products
Abstract
A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
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Citations
9 Claims
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1. A circuit for stabilizing soft bits in a bit stream, the circuit comprising:
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a first register adapted to receive an initial read of the bit stream, a second register adapted to receive a subsequent read of the bit stream, a comparator adapted to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register adapted to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator adapted to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit having a circuit for stabilizing soft bits in a bit stream, the circuit comprising:
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a first register adapted to receive an initial read of the bit stream, a second register adapted to receive a subsequent read of the bit stream, a comparator adapted to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register adapted to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator adapted to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads. - View Dependent Claims (6, 7, 8)
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9. A method of stabilizing soft bits in a bit stream, the method comprising the steps of:
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receiving an initial read of the bit stream, receiving a subsequent read of the bit stream, comparing the initial read of the bit stream to the subsequent read of the bit stream, producing a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and receiving the comparison string for multiple subsequent reads of the bit stream, and tracking positions of all soft bits detected during the multiple subsequent reads.
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Specification