Sub-micron high input voltage tolerant input output (I/O) circuit

• US 20080068050A1
• Filed: 10/31/2007
• Published: 03/20/2008
• Est. Priority Date: 01/09/2001
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan
• Application Number:
  US11/979,200
• Publication Number:
  US 20080068050A1
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

accepting an intermediate voltage;

providing a voltage derived from the power supply voltage or the intermediate voltage to the bias node when the power supply voltage is greater than a first predetermined value or the intermediate voltage is greater than a second predetermined value; and

providing a voltage derived from the pad voltage to the bias node when the power supply voltage is not greater than the first predetermined value and the intermediate voltage is not greater than the second predetermined value.

2. The method of claim 1, further comprising providing a voltage derived from the power supply voltage and the intermediate voltage to the bias node when the power supply voltage is greater than the first predetermined value and the intermediate voltage is greater than the second predetermined value.

3. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

providing a voltage derived from the power supply voltage to bias node when the power supply voltage is greater than a predetermined value; and

providing a voltage derived from the pad voltage to the bias node when the power supply voltage is not greater than the predetermined value.

4. The method of claim 3, wherein the predetermined value is about 3.3 Volts.

5. The method of claim 3, wherein the power supply voltage is accepted by a P-channel Metal Oxide Semiconductor (PMOS).

6. The method of claim 3, wherein the pad voltage is accepted by an N-channel Metal Oxide Semiconductor (NMOS).

7. The method of claim 3, wherein the power supply voltage is accepted by a P-channel Metal Oxide Semiconductor (PMOS) and wherein the pad voltage is accepted by an N-channel Metal Oxide Semiconductor (NMOS).

8. The method of claim 7, wherein the PMOS and the NMOS are connected at the bias node.

9. An apparatus for generating a bias voltage at a bias node, the apparatus comprising:

a first input for accepting a pad voltage from an input/output circuit;

a second input for accepting an output enable signal;

a third input for accepting a first input voltage; and

an output circuit for providing the first input voltage to the bias node when the output enable signal is at an enable value and for providing a voltage depending on the pad voltage to the bias node when the output enable signal is at a disable value.

10. The apparatus of claim 9, further comprising:

a fourth input for accepting a second input voltage,

wherein the output circuit provides a constant voltage equal to the first input voltage to the bias node until the pad voltage is equal to the first input voltage and provides an increasing voltage tracking the pad voltage when the pad voltage is not less than the first input voltage but is less than the second input voltage minus an offset voltage.

11. The apparatus of claim 10, wherein the offset voltage is equal to a threshold voltage of a transistor.

12. The apparatus of claim 10, wherein the offset voltage is equal to a threshold voltage of a P-channel Metal Oxide Semiconductor (PMOS).

13. The apparatus of claim 10, wherein the offset voltage is equal to a threshold voltage of an N-channel Metal Oxide Semiconductor (NMOS).